JPS58129554A - Error checking system - Google Patents

Error checking system

Info

Publication number
JPS58129554A
JPS58129554A JP57010595A JP1059582A JPS58129554A JP S58129554 A JPS58129554 A JP S58129554A JP 57010595 A JP57010595 A JP 57010595A JP 1059582 A JP1059582 A JP 1059582A JP S58129554 A JPS58129554 A JP S58129554A
Authority
JP
Japan
Prior art keywords
error
parity
memory
data
cpu11
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57010595A
Other languages
Japanese (ja)
Inventor
Kenji Hibi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57010595A priority Critical patent/JPS58129554A/en
Publication of JPS58129554A publication Critical patent/JPS58129554A/en
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy

Abstract

PURPOSE:To detect an error address without increasing a circuit, to prevent an error detection due to a noise, etc., and to elevate reliability, by confirming generation of a parity error again by a CPU, after the parity error has been generated. CONSTITUTION:To a CPU11, a main memory 12 which has stored a program and a data, and a control memory 17 which has stored a program for confirming and processing an error are connected. Also, a parity checking RAM13 is connected, and furthermore, a parity check generator 14 for writing a parity bit in the RAM when writing a data to the memory 12, and a parity information register 15 are connected. When a data has been read out from the memory 13 by this generator 14, its output and the output data of the RAM13 are parity- checked, and if there is an error, the CPU11 s interrupted through a line 19, confirmation of the error by the CPU11 is executed by a program of the memory 17, and an error due to a noise, etc. is prevented.
JP57010595A 1982-01-26 1982-01-26 Error checking system Granted JPS58129554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57010595A JPS58129554A (en) 1982-01-26 1982-01-26 Error checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57010595A JPS58129554A (en) 1982-01-26 1982-01-26 Error checking system

Publications (1)

Publication Number Publication Date
JPS58129554A true JPS58129554A (en) 1983-08-02

Family

ID=11754588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57010595A Granted JPS58129554A (en) 1982-01-26 1982-01-26 Error checking system

Country Status (1)

Country Link
JP (1) JPS58129554A (en)

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