JPS58125936A - Information communication system - Google Patents

Information communication system

Info

Publication number
JPS58125936A
JPS58125936A JP862182A JP862182A JPS58125936A JP S58125936 A JPS58125936 A JP S58125936A JP 862182 A JP862182 A JP 862182A JP 862182 A JP862182 A JP 862182A JP S58125936 A JPS58125936 A JP S58125936A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
devices
transmitting
receiving
reception
switchboard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP862182A
Other versions
JPH053181B2 (en )
Inventor
Teruo Komatsu
Katsuyoshi Maejima
Koichi Miyamoto
Takehiko Shibata
Kiyohisa Sugishima
Masayoshi Takahashi
Masahiko Takeuchi
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks

Abstract

PURPOSE:To have a quick countermeasure as a system as a whole without giving any load to the transmitting side, by performing the transmission and reception of information among plural terminals and then using a switchboard connected to a communication circuit of each terminal in case the reception is impossible at the receiving side. CONSTITUTION:Input transmitting part 12, 22-42 and receiving input parts 13, 23-43 are provided to terminal devices A-D distributed at each section. These parts 12-42 and 13-43 are connected to each other with communication lines 18, 28-48, respectively. At the same time, transmitting devices 15, 25- 45 and receiving devices 16, 26-46 of devices A-D are connected to a switchboard 50 via input and output communication lines 10, 20-40 and 11, 21-41 respectively. A demodulating circuit, a modulating circuit, a control part, a receiving command buffer, a transmitting command buffer, etc. are provided to each of the devices A-D. In case the receiving side is incapable of reception, a countermeasure is quickly given for a system as a whole by using the switchboard 50, a buffer, etc. and without giving any load to the transmitting side.
JP862182A 1982-01-22 1982-01-22 Expired - Lifetime JPH053181B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP862182A JPH053181B2 (en) 1982-01-22 1982-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP862182A JPH053181B2 (en) 1982-01-22 1982-01-22

Publications (2)

Publication Number Publication Date
JPS58125936A true true JPS58125936A (en) 1983-07-27
JPH053181B2 JPH053181B2 (en) 1993-01-14

Family

ID=11698008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP862182A Expired - Lifetime JPH053181B2 (en) 1982-01-22 1982-01-22

Country Status (1)

Country Link
JP (1) JPH053181B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8369307B2 (en) 2002-08-12 2013-02-05 Panasonic Corporation Receiving apparatus, transmitting apparatus and communication method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8369307B2 (en) 2002-08-12 2013-02-05 Panasonic Corporation Receiving apparatus, transmitting apparatus and communication method

Also Published As

Publication number Publication date Type
JPH053181B2 (en) 1993-01-14 grant

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