JPS58112136A - Multi-input signal comparator - Google Patents

Abstract

PURPOSE:To facilitate the monitor of faults for various types of data processor requiring high reliability, by realizing a multi-input signal comparator which has a fail-safe function. CONSTITUTION:The data fed from each final stage S8 is given to an exclusive OR gate EXOR G. The output of the EXOR G is ''0'' while the contents of stages S1-S8 of shift registers SRG1 and SRG2 are transmitted successively if the data having the same priority has the same logic value among data D11- D18 and D21-D28. Then an output (d) is set at ''1'' when the contents of the first stage S0 are fed. As a result, the data set at the front stage SL of a bilateral shift register BRG of a double-stage structure containing front and rear stages SL and SR is shifted to the rear stage SR in response to the output (d). Then the data obtained from the stage SR is set at ''1''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-input signal comparator that compares two systems of multi-input signals and detects a discrepancy between the two systems, and that has its own seven error characteristics. There is a tendency for processors such as microprocessors to be used in various fields, but in signal control equipment etc. that require high reliability and 7 error safety, the data processing systems used in the processors are multiplexed and Synchronized operation is carried out on the Maru-Ue, and monitoring is carried out to see whether the data of each system matches. is proposed.

However, the content of the same application has the drawback that a multiple ME circuit must be provided for each bit of each signal, and in the case of multiple bits, the structure becomes large-scale and the device is expensive. .

The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional method, and provides first and #I
Two shift registers are provided, data with contradictory logical values are set in each of the first stages, and each data of the signal to be compared is sent to each stage other than the first stage. , seven sets, each V7) register is caused to perform a p-shift operation using the same shift pulse, and each data obtained from the final stage of each shift register is compared by an exclusive i-OR circuit. After detecting a mismatch, this detection output shifts one piece of data set in at least a 2m bidirectional shift register from the previous stage to the next stage, and a reset pulse shifts one piece of data in the opposite direction. The present invention provides an extremely effective multi-input signal ratio aS, assuming that the data obtained from the subsequent stage always changes, and that the presence or absence of this change is detected by a detection circuit.

Hereinafter, the present invention will be described in detail with reference to a diagram showing implementation IP4.

Figure 1 is a block diagram showing the configuration! s2 diagram and 3rd
The figure is a tie-up chart showing the waveforms of various parts in 1mK.

to BO2, data D11 to Di, each of S bits;
, D,, ' ~ D
In response to the latch pulse LAP in FIG.
Data DIl to DI, D, -wD, are set to each stage 81 to S other than the first stage S in the shift registers 8RG, , and 8G. , a nine preset circuit (not shown in the figure) allows data of mutually contradictory logical m values '11 and 10' to be input to the latch pulse LA.
These data are sequentially transmitted from the shift pulse 5FPK shown in t42 (C), the shift pulse 5FPK, and the ill end R8m.

The data sent out from each final R8m is exclusive ORed (
Hereinafter, each data D, 1% D1 . ．． D.

~ D3.0 If the items with the same rank are the same - Rinakago, Tani RS
*-S While the contents of s are sent out sequentially, EXO
The output of R gate G shown in Fig. 2 (d) K is Tos at 'θ'.
As the contents of 1 [8.] are sent out, the output (d) becomes %
It becomes 11.

Then, to the front R8x of the bidirectional shift register Bl'LG, which has a two-stage configuration consisting of the front stage 5Lsp and the rear stage 8, '1', which had been set by a preset circuit not shown in the figure, is set.
According to the output (d), one piece of data indicating
) becomes '11.

The data indicating the latter stage 8m (D'l') is rounded and shifted in the opposite direction in response to the reset pulse R8PK generated next to the output (d), and accordingly, the data (f) becomes )',
By repeating the above operation every time signal (a) changes, data (f) becomes data D8. ~D,,,D,.

~l) ms of the same rank match @9, keep changing゛.

This change is given to a detection circuit such as an amplified detector,
The threshold at which the data (f) changes is determined by the relay K
L is moving I! to string.

On the other hand, as shown in Fig. 3, if p or data DI? +D□
If a mismatch occurs in the thresholds, the output (d) becomes 11' twice within one cycle of the signal (a), and the one data set at 111sL before the bidirectional shift pulser BRG is trapped from the rear stage 8m. It will be shifted,
Since the data in the same register BRG is only 'O',
After the data (f) changes once, it remains unchanged.

Then, the output of the amplified detector AD disappears and the relay KL is restored, so that the data DI is output.

~D1. ．． It is immediately detected that a mismatch occurs in any of D□ to Dll. Note that the shift registers 8RG, , 8RG, , ]1
ii If a % error occurs in any of the XOR gate G, bidirectional shift register BRG, etc., the data (f) will remain unchanged and the relay RL will recover, and the same will occur even if an abnormality occurs in the amplified detection @AD. Therefore, fail-safe performance as a whole is maintained.

Wait, shift register f! The number of stages of iRG, , 8RG, may be determined according to the number of bits of the signal (1), and the preset data to the first stage S is stored in each register S and G.

Similarly, the same data may be set in reverse in 8RG and 69, and the same data may be simultaneously preset to each stage 8L and 8m of the bidirectional shift register B and G, and the number of stages may be further increased depending on the detection time. Optional amplification test TI! L!
The present invention can be modified in various ways, such as using only the test aS instead of the i-man, and using the bird sensitivity relay as the relay KL.

As is clear from the above description, according to the present invention, a simple and inexpensive configuration realizes a multi-input signal ratio IR amount with fail-safe 4&, rounding, and various data processing devices that require high reliability. Abnormality #It shows a remarkable effect on the upper part of the eye.

[Brief explanation of the drawing]

The figure shows an implementation hook of the present invention, Figure ls1 is a block diagram of the configuration, and Figures 2 and 3 are diagrams showing the waveforms of each part in Figure 1. 8aG,,8RG,--a;y)-register,s. ...first stage, S, ...last stage, G...gxo
(exclusive OR game), BRG...bidirectional shift register, 8, 11...tllR18yi
...4ik stage, AD... amplified detector (detection circuit), D,, -D,,, D,, ~D,, @ # @ *
data. Figure 1 Procedural amendment (voluntary) Mr. Commissioner of the Patent Office ``°'''''sy...;,1
s"1, Indication of the case 1982 Patent Application No. 215649-2, Title of invention Multi-input signal comparator 3, Person making amendment

Claims (1)

[Claims] Shift registers 1 and 2, each having the same stage 1, in which data of mutually contradictory logical values is set to each first stage, and data is individually set to each stage other than the first stage; and an exclusive OR circuit that inputs each data sent from the final stage of the second shift register in response to the same shift pulse; A bidirectional shift register having at least two stages that shifts the one data to the previous stage and shifts the one data in the opposite direction in response to a reset pulse, and whether or not the data obtained from the subsequent stage of the bidirectional shift register changes. A multi-input signal ratio device comprising a detection circuit for detecting a signal.