JPS5811095B2 - How to use hand-made products. - Google Patents

How to use hand-made products.

Info

Publication number
JPS5811095B2
JPS5811095B2 JP14352175A JP14352175A JPS5811095B2 JP S5811095 B2 JPS5811095 B2 JP S5811095B2 JP 14352175 A JP14352175 A JP 14352175A JP 14352175 A JP14352175 A JP 14352175A JP S5811095 B2 JPS5811095 B2 JP S5811095B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
window
forming
etching
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14352175A
Other languages
Japanese (ja)
Other versions
JPS5267273A (en
Inventor
稲垣雄史
船山亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14352175A priority Critical patent/JPS5811095B2/en
Publication of JPS5267273A publication Critical patent/JPS5267273A/en
Publication of JPS5811095B2 publication Critical patent/JPS5811095B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は数100μmの厚さの半導体基板に数10μm
の大きさの通し穴(スルーホール)を高糖精度に形成す
る方法を提件するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor substrate with a thickness of several tens of micrometers.
The present invention proposes a method for forming through-holes with a high sugar precision.

半導体基板にスルーホールを形成する方法として従来、
ドリル、超音波加工、レーザ等を用いて機械的方法によ
って行われている。
Conventionally, as a method of forming through holes in a semiconductor substrate,
This is done mechanically using drills, ultrasonic processing, lasers, etc.

しかし乍らかか機械的方法によってはエツジ精度の良い
数μmの小さいスルーホールを形成することは困難であ
った。
However, it has been difficult to form through holes as small as several micrometers with good edge precision using mechanical methods.

本発明はかかる点から機械的方法によらずしかもエツジ
精度のよいスルーホールを得ることの出来るスルーホー
ル形成方法を提供することを目的とするものである。
In view of the above, it is an object of the present invention to provide a through-hole forming method that does not involve mechanical methods and can obtain through-holes with good edge precision.

そして本発明による方法は、半導体基板両面に酸化膜を
形成する過程、半導体基板表面上の酸化膜に所定の大き
さのスルーホールに対応する領域をとり囲む窓を形成す
る過程、該窓を介して半導体基板に該半導体基板よりエ
ツチングによる侵蝕が少ない不純物を拡散する過程、半
導体基板の裏面の表面に形成された窓の対応位置に窓を
形成する過程、該裏面に形成された窓より結晶方向依存
性のあるエツチング液によりエツチングを施す過程及び
半導体基板両面に形成された酸化膜を除去する過程を含
んでなることを特徴とするものである。
The method according to the present invention includes a step of forming an oxide film on both sides of a semiconductor substrate, a step of forming a window surrounding an area corresponding to a through hole of a predetermined size in the oxide film on the surface of the semiconductor substrate, and a step of forming an oxide film on both sides of a semiconductor substrate. a process of diffusing impurities into the semiconductor substrate that is less corroded by etching than the semiconductor substrate; a process of forming a window at a position corresponding to a window formed on the back surface of the semiconductor substrate; This method is characterized in that it includes a step of etching with a dependent etching solution and a step of removing an oxide film formed on both surfaces of the semiconductor substrate.

以下本発明の実施例を図面に従って説明する。Embodiments of the present invention will be described below with reference to the drawings.

第1図乃至第5図は本発明の方法を構成する過程を順次
示している。
FIGS. 1 to 5 sequentially illustrate the steps constituting the method of the present invention.

第1図は半導体基板Siの両面に酸化膜を形成しその一
部に窓を設ける過程を示している。
FIG. 1 shows the process of forming oxide films on both sides of a semiconductor substrate Si and providing a window in a part of the oxide film.

半導体基板Siは板面方向が略々100面(この100
面とは100面、010面、001面、100面・・・
・・・を総称する。
The semiconductor substrate Si has approximately 100 planes in the board surface direction (this 100
The faces are 100 faces, 010 faces, 001 faces, 100 faces...
...is a general term.

)となるごとく切り出した例えばシリコン・ウェハであ
る。
), for example, a silicon wafer cut out.

この両面を酸化して酸化物層この場合にはSiO2層を
形成する。
Both surfaces are oxidized to form an oxide layer, in this case a SiO2 layer.

次いで表面に形成された酸化物層に所定のスルーホール
の大きさに対応する領域A(第1図口は上面から見た図
)をとり囲む窓Bをエツチングにより形成する。
Next, a window B is formed in the oxide layer formed on the surface by etching, surrounding a region A (the opening in FIG. 1 is a view from the top) corresponding to the size of a predetermined through hole.

次いで第2図に示すように表面に形成された窓Bを介し
て不純物μPを拡散によって半導体基板Siに数μmの
深さで注入する。
Next, as shown in FIG. 2, an impurity μP is implanted into the semiconductor substrate Si to a depth of several μm by diffusion through a window B formed on the surface.

この時表面の酸化物層SiO2及び窓B上に酸化物層S
iO2が形成される。
At this time, an oxide layer S on the surface oxide layer SiO2 and window B
iO2 is formed.

ここで不純物uPとして後述する過程によって明らかに
なるように半導体基板に対するよりもエツチングによる
侵蝕が少いものであることが必要である。
Here, the impurity uP needs to be less corrosive by etching than the semiconductor substrate, as will become clear from the process described later.

例えば2×10−19cm−3以上の濃度のほう素B(
Bo−ron)が使用され半導体基板に窓Bより数μm
の深さに拡散注入されることが必要である。
For example, boron B (
Bo-ron) is used on the semiconductor substrate several μm from the window B.
Diffusion implantation is required to a depth of .

第3図は半導体基板Siの裏面に形成された酸化物層B
iO2に窓Bの対応位置に窓Wを形成することを示して
いる。
Figure 3 shows an oxide layer B formed on the back surface of a semiconductor substrate Si.
It is shown that a window W is formed in iO2 at a position corresponding to window B.

次いで第4図に示す過程においてエツチング液例えばA
、P、W(エチレンジアミン17C,C,、パイロカテ
コール3gr、水8C,C,よりなる溶液)或いはNa
CH,KOH等の塩基性溶液にて窓Wを介してエツチン
グを施すことにより錐体状の凹部Hが裏面から形成され
る。
Next, in the process shown in FIG.
, P, W (solution consisting of ethylenediamine 17C,C, pyrocatechol 3gr, water 8C,C) or Na
By etching through the window W with a basic solution such as CH or KOH, a cone-shaped recess H is formed from the back surface.

ここで例えば、A、P、Wは単結晶シリコンに対しその
100軸(この100軸とは100軸、012軸、00
1軸、100軸・・・・・・を総称するものとする)方
向に最も大なる侵蝕性を有し、これに次いで110軸(
この110軸とは、110軸、101軸、011軸、1
10軸・・・・・・を総称するものとする。
For example, A, P, and W are the 100 axes of single crystal silicon (the 100 axes are the 100 axis, 012 axis, 00 axis).
1 axis, 100 axis...) direction has the greatest erosiveness, followed by 110 axis (
These 110 axes are 110 axis, 101 axis, 011 axis, 1
The 10 axes... shall be collectively referred to as the 10 axes.

)、111軸(この111軸、111軸、111軸、・
・・・・・を総称するものとする。
), 111 axis (this 111 axis, 111 axis, 111 axis,
... shall be collectively referred to as...

)の順に侵蝕性が小となる結晶学的性質を有することが
知られている。
) is known to have crystallographic properties in which corrosiveness decreases in the order of

故にシリコンをその板面が100面となるごとく切出し
、この面より窓Wを介してA、P、W等の結晶方向依存
性のあるエツチング液によりエツチングすることにより
このエツチング液によって侵され難い111面が露呈さ
れることにより第4図に示すごとき錐体状の凹部Hが形
成される。
Therefore, by cutting out a piece of silicon with 100 planes and etching it from this plane through the window W with an etching solution that is dependent on the crystal direction, such as A, P, W, etc., it is difficult to be attacked by this etching solution111. By exposing the surface, a cone-shaped recess H as shown in FIG. 4 is formed.

尚、前述のように部分uPは不純物拡散によって半導体
基板に較べ侵蝕され難くなっているので第4図の如く残
される。
As mentioned above, the portion uP is left as shown in FIG. 4 because it is less susceptible to corrosion than the semiconductor substrate due to impurity diffusion.

次に半導体基板Siの両面に形成されている酸化物層S
iO2をエツチング等により除去することによって第5
図に示すように半導体基板Siにスルーホールが形成さ
れることになる。
Next, an oxide layer S formed on both sides of the semiconductor substrate Si
By removing iO2 by etching etc., the fifth
As shown in the figure, through holes are formed in the semiconductor substrate Si.

以上の過程により機械的方法を用いずエツジ精度の高い
スルーホールを形成することが出来る。
Through the above process, a through hole with high edge precision can be formed without using mechanical methods.

即ちエツジ精度は表面の酸化物層SiO2上へ窓Bを形
成する際のスルーホールの大きさに対応する領域Aをフ
ォトエツチング等により精度よく行えばよく機械によっ
てスルーホールを形成するに較べはるかに精度よく行わ
れることはいうまでもない。
In other words, the edge accuracy can be improved by photoetching the area A corresponding to the size of the through hole when forming the window B on the surface oxide layer SiO2, and it is much better than forming the through hole by machine. Needless to say, this is done with great precision.

同以上の説明で半導体基板としてシリコンSiを例にと
ったがエツチング液組成を適切に選ぶことにより本発明
はシリコン半導体基板を対象とすることに限定されない
Although silicon Si was used as an example of the semiconductor substrate in the above description, the present invention is not limited to silicon semiconductor substrates by appropriately selecting the composition of the etching solution.

更に本発明によってエツジ精度の高いスルーホールを形
成することが出来るので本発明によって得られるスルー
ホールをウェハーの一部に形成することにより半導体装
置形成においてスルーホールを通過する光量を検知して
位置合せを行うということに利用して大なる効果が得ら
れる。
Furthermore, the present invention makes it possible to form through-holes with high edge precision, so by forming the through-holes obtained by the present invention in a part of a wafer, it is possible to detect the amount of light passing through the through-holes and perform alignment during the formation of semiconductor devices. You can get great results by using it to do this.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第5図は本発明方法の一実施例過程を示す。 図においてSiは半導体基板、Aは所定の大きさのスル
ーホールに対応する領域、Bは領域Aをとり囲むエツチ
ング窓、Wは裏面に形成されるエツチング窓。
1 to 5 show the steps of an embodiment of the method of the present invention. In the figure, Si is a semiconductor substrate, A is a region corresponding to a through hole of a predetermined size, B is an etching window surrounding region A, and W is an etching window formed on the back surface.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板両面に酸化膜を形成する過程、半導体基
板表面上の酸化膜に所定の大きさのスルーホールに対応
する領域をとり囲む窓を形成する過程、該窓を介して半
導体基板に該半導体基板よりエツチングによる侵蝕が少
ない不純物を拡散する過程、半導体基板の裏面の表面に
形成された窓の対応位置に窓を形成する過程、該裏面に
形成された窓より結晶方向依存性のあるエツチング液に
よりエツチングを施す過程及び半導体基板両面に形成さ
れた酸化膜を除去する過程を含んでなることを特徴とす
る半導体基板にスルーホールを形成する方法。
1 A process of forming an oxide film on both sides of a semiconductor substrate, a process of forming a window surrounding an area corresponding to a through hole of a predetermined size in the oxide film on the surface of the semiconductor substrate, and a process of forming an oxide film on both sides of the semiconductor substrate, and forming a window surrounding a region corresponding to a through hole of a predetermined size, and applying the semiconductor to the semiconductor substrate through the window. A process of diffusing impurities that is less corroded by etching than the substrate, a process of forming a window at a corresponding position to a window formed on the back surface of the semiconductor substrate, and an etching solution that is more dependent on the crystal direction than the window formed on the back surface. 1. A method for forming a through hole in a semiconductor substrate, the method comprising the steps of etching by etching and removing an oxide film formed on both sides of the semiconductor substrate.
JP14352175A 1975-12-01 1975-12-01 How to use hand-made products. Expired JPS5811095B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14352175A JPS5811095B2 (en) 1975-12-01 1975-12-01 How to use hand-made products.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14352175A JPS5811095B2 (en) 1975-12-01 1975-12-01 How to use hand-made products.

Publications (2)

Publication Number Publication Date
JPS5267273A JPS5267273A (en) 1977-06-03
JPS5811095B2 true JPS5811095B2 (en) 1983-03-01

Family

ID=15340662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14352175A Expired JPS5811095B2 (en) 1975-12-01 1975-12-01 How to use hand-made products.

Country Status (1)

Country Link
JP (1) JPS5811095B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0581405U (en) * 1992-04-06 1993-11-05 日本軽金属株式会社 shelter

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57182449A (en) * 1981-05-07 1982-11-10 Fuji Xerox Co Ltd Forming method of ink jet multinozzle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0581405U (en) * 1992-04-06 1993-11-05 日本軽金属株式会社 shelter

Also Published As

Publication number Publication date
JPS5267273A (en) 1977-06-03

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