JPS58106826A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the reduction of the number of effective wafer chips and thus reduce the restriction of element arrangement in a chip, by forming positioning patterns in the region which isolate chips from chips. CONSTITUTION:As the mask for the first photoetching process (PR process), cross patterns A1L and A1R are put in the scribe line region at the position of mask symmetry right and left. As the second PR process mask, patterns B1L, B1R, B2L, and B2R are put in the scribe line region. Hereupon, the patterns B1L and B1R are arranged so that the cross patterns A1L and A1R which are patterned by the first PR process mask may be put in, and the patterns B2L and B2R are patterns serving as the standard of the third PR process mask. In the same manner below, patterns C2L, C2R, C3L, and C3R as the third PR process mask and patterns D3L and D3R as the forth PR peocess mask are put. Then, PR processes are advanced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for aligning a non-light mask in a method for manufacturing semiconductor devices such as integrated circuits, which requires photolithography a number of times in succession.

Conventionally, this type of alignment pattern is shown in FIG. 1 by providing marked areas IL and IR and forming an alignment pattern there (9), and then forming an alignment button area 3 within one chip as shown in FIG. It was set up. By providing the alignment pattern area in this manner, the effective chip area within the wafer is sacrificed, and the arrangement of elements within the chip may be restricted due to the provision of the alignment pattern area within the chip.

The present invention solves the above-mentioned drawbacks by forming an alignment pattern in the area separating the chips, eliminates the reduction in the effective number of chips on the wafer, and reduces restrictions on the arrangement of elements within the chip. Have eye contact. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

The scribe area is an area where chips within a wafer are separated using a diamond and a tycer.
It is designed to have a width of 0 m or more. The area 5 where this scribe area 2 intersects has an L-shape as shown in FIG. 3, and has nine patterns.

``1s'll*a4'' has a distance of xl from the chip area in the scribe area, and the patterns are located at a distance of X from each other. Width C
By entering pattern b, alignment is performed. L-shaped pattern spacing X.

The relationship between the width C of the cross pattern C and the width C of the cross pattern C differs depending on the required accuracy of alignment. In other words, if the value of xl-c is small, it
The accuracy will be higher.

If an element is manufactured using 4PR using this pattern, each mask will be as shown in Figure 4.As a mask for the first photolithography process (hereinafter referred to as PR process), the symmetrical positions of the mask will be used. Cross pattern At L , At m
(Fig. 4 GA)) o As the 2nd PR process mask, as shown in Fig. 4-
, insert the 3sn, Bab, and Ban patterns into the second and third line areas. ζThis is the pattern BIL.

BIR@IPR The cross-shaped patterns ASL, AtB formed by the pattern area using the mask for the IPR process are arranged so as to fit therein, and the patterns BIL, H! B
is a reference pattern for the mask for the third PR process.

Similarly, as shown in FIG. 4 (Q), putter y C2L, CIR, CIL, CI
As shown in FIG. 4, patterns 1) at, , Dsm are placed on R as a fourth PR process mask. And pattern HIL.

In order for DIR to enter the pattern Ctz, CsR, the putter ycst,, Cs1z is changed to p ++ y DSL, D
Proceed through the P process to enter LR.

The shape arrangement position of the pattern described here is merely an example and is not limited thereto.

As described above, by providing an alignment pattern in the scribe area, the effective number of chips on the wafer is prevented from being reduced, restrictions on the arrangement of elements within the chip are reduced, and since the alignment pattern does not remain within the chip, information regarding the manufacturing method is We can provide devices that will not be missed.

4. a! 1 Brief explanation of lffi Figure 1 is a plan view showing how an alignment pattern area is deposited in a silicon wafer.0 Figure 2 is a diagram showing how an alignment pattern area is provided in a chip and the scribe area. FIG. FIG. 3 is an enlarged plan view of the alignment pattern provided in the scribe area of the embodiment of this invention, and FIG. 4 is a diagram showing an embodiment of the mask eyelid pattern when an element is manufactured by 4PR. In a certain diagram, %IL@IB, 3... alignment pattern area, 2... scribe area, 4...
・Pad, 5...Scripe area, 6...
・・Half-body chip, AsL, AIIIH le, Btu, B
at, , Ba1L, Cl, C**, Cab, Csn.

DSL, DIR...0 Figure 1 Koshirae 2 Figure (A) (B) Hoko which is a matching pattern. .

Tsukasa (D)

Claims (1)

[Claims] In a semiconductor device manufacturing method that requires photo-etching operations many times in succession and simultaneously forms a large number of semiconductor devices, the alignment pattern of the non-light mask of the semiconductor device is used to align the semiconductor devices with each other. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is formed in separate regions.