JPS58105376A - Reading system of service interuption time - Google Patents

Abstract

PURPOSE:To know the time of service interruption and at the same time to ensure a quick reset to the normal time, by stopping the working of a clock counter to hold the service interruption time data when the service is interrupted and counting the number of clocks equivalent to the period of service interruption by means of a different high-speed clock counter. CONSTITUTION:The time of service interruption is known for a data collector, and the processing items which are missed in the period of service interruption. In this case, a time counter CTR1 counts clocks and delivers a time data. When a service interruption is detected, the counter CTR1 stops its counting of clocks and holds the time of service interruptin. A counter CTR2 counts high-speed clocks (1-minute clocks) in place of the CTR1. Then the contents (the number of clocks equivalent to the period of service interruption) of the counter CTR2 are read and applied to the counter CRT1. Thus the time can be reset to the present normal time.

Description

[Detailed Description of the Invention] This invention relates to a power outage time reading method in the data collection device i#, in which the processing unit captures the power outage time to recognize missing processing items during the power outage period. It is something.

For example, as shown in FIG. 1, the data collection device includes a processing unit 1. Memory 2. It has an input/output control section 5 and a clock section 4, the clock section 4 is uninterrupted by a battery or the like, and the processing section 1 collects data at predetermined time intervals according to time data from the clock section 4. In such a data collection device, when a power outage occurs, only the hour hand section 4 continues to operate because it is uninterrupted, but the other sections stop operating because of their large power consumption. Then, when the power is restored and the clock section 4 is operating normally, the processing section 1 can continue processing again.

However, depending on the data collection device, it may be necessary for the processing section 1 to recognize the missing processing entry during the power outage period. In that case, it is necessary for the processing unit 1 to know the power outage time.

Therefore, it is conceivable to make the memory 2 uninterrupted as shown in FIG. 2, for example. That is, time data is written from the clock section 4 into the memory 2 under the control of the processing section 1, and the time data in the memory 2 is updated at regular intervals. Therefore, when a power outage occurs, writing of time data to the memory 2 is stopped, so that the contents of the memory 2 indicate the time of the power outage.

This power outage time can be read by the processing unit 1 when the power outage is restored.

This conventional example requires uninterrupted power supply to the memory 2 and time update processing under the control of the processing unit 1, and requires a backup power supply corresponding to the capacity of the memory 2 and the processing load on the processing unit 1 to be large. There are drawbacks that must be met.

In addition, as shown in Fig. M5, clock parts 4a and 4b are provided for uninterrupted power outage.The clock part 4a operates in the same manner as the clock part 4 in FIG. When the clock section 4b is detected, the operation of the clock section 4b is stopped and the power outage time is held, and when the power outage is recovered, the processing section 1
Since the time of power outage is read from , there is no need to update the time to the memory 2. However, there is a drawback that two clock sections 4a and 4b must be provided, and that the processing section 1 cannot recognize the two clock sections 4a and 46, respectively.

An object of the present invention is to make it possible to maintain power outage time with one clock unit. Examples will be described in detail below.

Figure 4 is a block diagram of main parts of an embodiment of the present invention.
cTR1 is a gate circuit that outputs time data in response to a read signal from the processing section, and cTRl is a gate circuit that outputs time data based on a read signal from the processing section, and cTRl is a clock unit of 1 minute, 10 minutes, or 1 hour, for example.

A time counter that outputs time data around 10 o'clock, O
20 is an oscillator that outputs a reference double-speed clock, 1) V is a frequency dividing circuit that divides the high-speed clock and outputs, for example, a 1-minute clock, DET is a power failure detection unit, FF1° and FF2 are flip 70 knobs, and CTR2 is a power failure A counter that counts up the 1-minute clock during the period and counts down the high-speed clock when recovering from a power outage. 01 to G4 are AND circuits, and G5.
6 is an OR circuit, and G7If'i is a NOR circuit.

FIG. 5 is a diagram showing the operation, and (α) to (j) show waveforms of examples of signals α to i at each part in FIG. 4.

Shift flip-flop FF according to read signal f from processing section
1 is reset, and the 1-minute lock b from the frequency divider circuit DV becomes the count clock d of the counter CTR1 via the AND circuit G1 and the OR circuit G5,
The contents of the count 11 are time data as described above, and the gate circuit G is opened by the read signal f, and the time data is read by the processing section.

If a power outage occurs at time t1, the detection signal a from the power outage detection unit DET becomes @1#, and the flip-flop FF
1 is set. Therefore, the Q terminal output C is shown in Figure 5 (1).
), the output of the NOR circuit GV' becomes "0" and the AND circuit G1 is closed, and the Q terminal output g of the flip-flop FF2 is also @IO"'.
Count clock d is no longer applied to counter CTR1. That is, the power outage time is held in the counter CTR1.

Also, since the Q terminal output C of the 7-lip flop FF1 becomes 11#, the 1-minute lock b becomes the AND circuit G3. It becomes a count clock via the OR circuit G6. Also, since the Q terminal output of the flip-flop FF2 is "1", the counter CTR2 enters the $11 up count mode, and the count clock - tube counts up. That is, one minute lock b is counted instead of time counter CTR1.

When the power is restored at time t2, the detection signal aid shown in Fig. 5 (→
It becomes "0" as shown in . After time t2, the processing unit reads the power outage time by the signal f, which causes the flip-flop FF1 to be activated.
is reset, and the Q terminal output c becomes "H@o".Flip-flop FF2 is also set, and the Q terminal output g becomes "
1", terminal output (is "0"), counter CTR2
is in down count mode.

Therefore, the high-speed clock is AND circuit G2. It becomes the count clock d via the OR circuit G5, and the AND circuit G
4. It becomes a count clock via the OR circuit G6.

Counter CTR2 counts up the 1-minute clock during the power outage period, and downcounts the high-speed clock when the power is restored. When the borrow signal k is output, the 7-lip-flop FF2 is reset, and the Q terminal output g becomes @0#. Naυ
Since the flip-flop FF1 is in the Morino set state, the AND circuit G1 is opened, the AND circuits 02 to G4 are closed, and the one-minute clock b becomes the count clock d of the time counter CTR1. That is, as many high-speed clocks as the number of 1-minute locks b added to the counter CTR2 during the power outage period are added to the time counter CTR1 at the same time as the power is restored, the time counter CTR1
The contents of will again indicate normal time data.

As explained above, Fujuisha, a time clock/clock that counts the clock of 1-minute lock b4 and outputs time data.
CTR1 and time counter CTR1 when a power outage is detected.
Stop counting the clock and set the time counter CTR.
In place of 1, it is equipped with a counter CTR2 that counts a clock such as a 1-minute lock b, and when the power is restored, the processing unit reads the power outage time data held in the time counter CTR1, and the high-speed clock is activated by the count content of the counter CTR2. In addition to the time counter CTR1, the time counter crrt11d can output normal time data, and at the time of a power outage, can hold the power outage time data by stopping the clock count. In addition, upon recovery from a power outage, it is possible to return to the normal time by counting high-speed clocks corresponding to the number of clocks corresponding to the power outage period. For example, time counter CT
When R1 outputs time data by counting 1-minute clocks, the high-speed clock is set to 100f#z, for example.
Then, even in the case of a 10-hour power outage, the time counter C
It only takes 6 mS for TR1 to return to the normal time according to the high-speed clock count.
11i of 1 minute clock! It is possible to return to normal time within the i1 period. Further, the present invention is not limited to only the S configuration shown in FIG. 4, and various logical configurations can be adopted.

[Brief explanation of the drawing]

1, 2, and 6 are block diagrams of main parts of a data collection device equipped with a conventional clock section, FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is an operation explanatory diagram. It is. CTR1 is a time counter, G is a gate circuit, O20 is an oscillator, Dr is a frequency dividing circuit, CTR2 is a counter, FF1.
FF2 is a 7-lip flop, and I)ET is a power failure detection section. Patent applicant Fujitsu Limited

Claims (1)

[Claims] In a system in which a power outage time is held and the power outage time is read by a processing unit when the power outage is recovered, there is provided a time counter that counts a clock and outputs time data, and a time counter that stops counting the clock of the time counter upon detection of a power outage. a counter that holds power outage time data and counts the clock instead of the time counter; the processor reads the power outage time data held in the time counter when the power outage is recovered; and the count contents of the counter A patented power outage time reading method that adds a high-speed clock to the time counter.