JPS58105312A - Constant voltage circuit - Google Patents

Constant voltage circuit

Info

Publication number
JPS58105312A
JPS58105312A JP20428581A JP20428581A JPS58105312A JP S58105312 A JPS58105312 A JP S58105312A JP 20428581 A JP20428581 A JP 20428581A JP 20428581 A JP20428581 A JP 20428581A JP S58105312 A JPS58105312 A JP S58105312A
Authority
JP
Japan
Prior art keywords
voltage
transistor
circuit
output
constant voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20428581A
Other languages
Japanese (ja)
Inventor
Mitsutake Sato
佐藤 光勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20428581A priority Critical patent/JPS58105312A/en
Publication of JPS58105312A publication Critical patent/JPS58105312A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33538Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type
    • H02M3/33546Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current

Abstract

PURPOSE:To increase both speed of response as well as accuracy of output electric power for a constant voltage circuit which sets an ON time of a transistor and then supplies the constant voltage to a load, by setting the ON time of the transistor by the output of the 2nd comparing/amplifying means. CONSTITUTION:The voltage supplied to a load RL is detected by a voltage detecting circuit 7 and delivered to a differential amplifier 10 to be compared with the reference voltage E0. Then this differential is amplified and delivered to a differential amplifier 9. The amplifier 9 compares the voltage supplied from the amplifier 10 with the voltage to be applied to a resistance R2, and this differential is amplified and delivered to a pulse width control circuit 8. The circuit 8 sets by the output of the amplifier 9 the time width to be applied to the voltage of a transistor Q. As a result, an unstable state never occurs to a feedback system having an order delay element with a high level secured for the gain. Therefore the overall gain of the circuit can be increased.

Description

【発明の詳細な説明】 (ml 発明の技術分野 本発@は田力威に嚢處ダイオード、インダクタンス及び
コンデンサからなる平IIl崗路を持ら、負荷に定電圧
管供鎗すゐ定゛亀圧−路に係り、臀に応答速度及び5i
!嶌圧化槽置を改畳しt麓嶌圧關路Ellする。
[Detailed Description of the Invention] (ml Technical Field of the Invention The present invention is based on the present invention, which has a parallel circuit consisting of a capacitor diode, an inductance, and a capacitor, and provides a constant voltage tube to the load. -Response speed and 5i on the buttocks
! Renovate the pressure tank and install the pressure tank at the foot of the mountain.

4− 技術O背景 通信の分野及びその伽の分野でMhられる鍮電圧−路と
して、応答遮駅が遍く、−麟か安定で1/IIKの良−
40が嘗に装車されて−る@榛) 従来技術と問題点 11!IIQは做米の*電圧#A路の一儂或例を示すQ
はトランジスタ、01は;ンデンデ、Lriインダクタ
ンス%RLは負荷、lはパルス−#−−路、Sは平f#
−路、$はIEJIII増暢−1会は亀圧慎出−錯であ
る。
4- Technology O Background In the field of communication and the field of communication, the response voltage is ubiquitous, and the response is stable and as good as 1/IIK.
40 has been installed in the past @Haru) Conventional technology and problems 11! IIQ is an example of the *voltage #A path in the US.
is a transistor, 01 is; ndende, Lri inductance %RL is a load, l is a pulse-# path, S is a flat f#
- route, $ is IEJIII Masunobu-1 meeting is Kamiotsu Shinde-complex.

塵s#Igは従来の定電圧−路のボード−凶匈で6る・
悶Kj?いて、慣−fは周駅款、続−Gは列置。
The dust s#Ig is 6 times with the conventional constant voltage - road board -
Agony Kj? , custom-f is the station clause, and continuation-G is the arrangement.

#1@φは位相角で6jysφ1及び−1は位相駿畜。#1@φ is the phase angle and 6jysφ1 and -1 are the phase angles.

Gl&2FG、は利傅傘裕でるる〇 塵8−は値米の定電圧1踏の観の−侮戚狗倉示す図であ
る。図において、第1図とIIfJ−査号及び同−記号
のものは同一の装置Ilまたは素子を表わし、D、はダ
イオード、ル□及びB、は抵抗、0.はコンデンサ、!
6はパルス−@岬−路、6は差動増幅器で6る〇 筐ず、絽1図の定電圧−路の動作を説明する・パルス市
1jm回路lからトランジスタ(hのペースに電圧が加
わると、トランジスタqはオンとなる0このことKよシ
、入力電muよりト2ンスT、〇−久巻4N、−12ン
ジスタqのコレクタートランジスタQのエミッメー人力
電aI!というループで電流が流れる・またトランジス
タQのエイνり電流はダイオードDxt”通して、トラ
ンスTl0−久0SNIKも流れる。この時、−次畳−
N1−N、で発生する電圧か二次巻fiN−に#起され
る0この電圧は電流ダイオード及び平#回路4によ)平
滑化されて負荷RLK供給される0 パルス幅側#1&&1JIIlからトランジスタQのベ
ースに電圧が加わらなくなると、トランスTlの一久4
m’1llNllN、には1L癒が流れなくな〕、トラ
ンスT、の電圧は反転し、ダイオードD、が導通し、ト
ランスがリセットされる・しかし、トランジスタQl#
、をンの時に平滑回路2で一起される電圧が平滑化され
ているので、トランジスタQかオフとなっても負荷RL
には電圧が供給される。
Gl & 2FG, is a diagram showing the view of constant voltage 1 step of price rice. In the figure, those in FIG. 1 and IIfJ and the same symbol represent the same device Il or element, D is a diode, □ and B are resistors, 0. is a capacitor!
6 is a pulse-@misaki-route, 6 is a differential amplifier, and 6 is a differential amplifier. , the transistor q turns on. 0 This means that the current flows from the input voltage mu to the input voltage mu to the collector transistor Q of the collector transistor Q of the transistor q.・Also, the current of the transistor Q flows through the diode Dxt and the transformer Tl0-K0SNIK. At this time, - next voltage -
The voltage generated at the secondary winding fiN- is smoothed by the current diode and the flat circuit 4) and supplied to the load RLK. When no voltage is applied to the base of Q, the transformer Tl
1L current no longer flows through m'1llNllN,], the voltage of transformer T is reversed, diode D is conductive, and the transformer is reset. However, transistor Ql#
, the voltage generated by the smoothing circuit 2 when the transistor Q is turned on is smoothed, so even if the transistor Q is turned off, the load RL
is supplied with voltage.

次11C$1図の定電圧−路の負荷RLK屋電圧電圧給
するための制御系を説明する・負荷几りに〃口わる電圧
を電圧検出(ロ)路4(但し、入力、出力アース共通の
場合は必襞としない)で検出し、差−増@a)IK出力
する・差動増幅器8では電圧検出回路4からの電圧値と
基準電圧E、とt比−し、その差分を増幅してパルス幅
制御回161に出力する。
Next, we will explain the control system for supplying voltage to the load RLK house voltage of the constant voltage path in Figure 11C$1. Voltage detection (b) for the voltage depending on the load (however, input and output ground are common) In the case of , the voltage value from the voltage detection circuit 4 and the reference voltage E are t-ratioed, and the difference is amplified. and outputs it to the pulse width control circuit 161.

パルス幅制御回路1では1IIIII増幅−8の出力に
よ)、トランジスタqのペースに211Jわる電圧の時
間幅を設定する。
In the pulse width control circuit 1, the time width of the voltage corresponding to the pace of the transistor q by 211 J is set by the output of the 1III amplifier -8.

すなわち、トランジスタQlのオン及びオフ時開を負荷
RLK21Elわる電圧値により設定することによりて
、負荷RL4C定電圧を供給するものである・次K11
l劇の定電圧回路の動作を説明する。
That is, by setting the on/off state of the transistor Ql according to the voltage value of the load RLK21El, a constant voltage of the load RL4C is supplied.Next K11
I will explain the operation of the constant voltage circuit.

このmsamio定電圧回路は、薦1図の定電圧回路の
劃−系tIIjIp除いたものに、トランスTlの二仄
醤趣として、二久巻巌N、を設け、ダイオードD6、鉱
抗凡8、コ/デンサO,抵恍Rat纂易図に示すすなわ
ち、この定電圧回路は、二次畳−N、に1起される電圧
をダイオードD4.抵抗R1,R1mコンデンサC1で
平均化し、とのJF均化した電圧と基準電圧とをM#増
暢#6で比収し、その着分を増幅して出力し、この出力
に1シバルスー劇#−踏襲でトランジスタqのベースに
加える電圧の時間幅f:数設定る。
This msamio constant voltage circuit is the same as the constant voltage circuit shown in Figure 1, except for the voltage system tIIjIp, and is provided with Nikumaki Iwao N as a second addition to the transformer Tl, and a diode D6, a mine 8, In other words, this constant voltage circuit converts the voltage caused by the secondary voltage -N into the diode D4. The voltage equalized by the resistor R1, R1m and the capacitor C1 and the reference voltage are collected by M# amplification #6, and the output is amplified and output. - Set the time width f of the voltage applied to the base of the transistor q: number.

すなわち、トランジスタQのオン及びオフ#閾を暑巌亀
圧に工)設定するものであったOしかしながら、かかる
促米の定電圧回路の#成では以下の欠点か生じる0 皐l凶にボす定電圧回路では、伝趨費素として十階&g
I#iI内のインダクタンスL及びコンデン10を持つ
几めに、伝2m賛本か二次通れ賛系となる0今s sl
 ”凶に示す定電圧回路のボード−幽か第1!Q(−の
■−第11IA(bjK示す特性だったとする0この時
、安定度を知るための利得余裕及び位相余裕はそれぞれ
Gl−φlである0利侍余袷がjgz図(b)に示す位
相角特性が一180’となった周IN数で、311図(
dに示す利得が負であシ、位相余裕か第8図1mlに示
す利得特性でO(dBJとなったMl改数で第swJ偽
)に示す位相角特性が−130エフ小さければその回路
は安定であるといえる0また、回路の応答速度はループ
の利得が嬌いほど速くなる0しかし、応答速度を速くす
るために1票8図(−の■に示すように利得を^くする
と、十分な位相余裕及び利得余裕がとれないため、回路
の安定性をそこなうことになる0すなわちS81図のf
fi[圧回路では安定性が良いtま応答速度を運くする
ことができないという欠点かあつ7t。
In other words, the ON and OFF thresholds of the transistor Q were set to the highest voltage. In a constant voltage circuit, the tenth order &g is used as a conduction cost element.
By having an inductance L and a capacitance 10 in I#iI, it becomes 0s sl which is 2m or secondary.
``The board of the constant voltage circuit shown in the dark - 1st! , the phase angle characteristic shown in the jgz diagram (b) is 1180', and the number of laps is 311 (
The circuit is 0 can be said to be stable.Also, the faster the loop gain, the faster the response speed of the circuit0.However, in order to increase the response speed, if you increase the gain as shown in Figure 8 (-), 0, that is, f in the S81 diagram, which impairs the stability of the circuit because sufficient phase margin and gain margin cannot be taken.
The disadvantage of a pressure circuit is that it cannot provide high stability and response speed.

第8図の定電圧回路では、トランスT□O会−電圧を検
出しているため、出力の電圧安定!II&が侍にくいと
いう欠点があった。
In the constant voltage circuit shown in Figure 8, the voltage of the transformer T□O is detected, so the output voltage is stable! The drawback was that II& was difficult to use as a samurai.

(dJ  発明の目的 不発明は、かかる従来の欠点′fI:点み、十分な位相
傘11i及び利得余裕を得て、回路の安定性を良くする
とともに、にム答が運く、出力電圧tII縦の艮い芝瓢
圧ig1繕を提供することを目的とする0(eJ  見
開の4II或 トランス及び販トランスの一久巷III!−にトランジ
スタ及び威トラ/スの二仄醤M14i1に整流ダイオー
ド−インダクタンス−コンデンサからなる平Il#回路
【もち、出力電圧に19、該トランジスタのオン時閾t
″設定して負荷に定電圧を供給する定電圧lP!l路に
おいて、坂出力電圧と所定の基準電圧とを比軟し、JJ
II−して出力する箒lの比較増幅手板及び該slの比
値増−手獣の出力と咳トランスの巻−区圧km流平均化
した電圧とt比較し、増幅して出力する第3の比砿壇嘱
手獣及び該第2の比#Rjw−手獣の出力にxDsaト
ランジスタのオン時闇kI!I+!定する十獣を設は九
ことt脅値とするものでめる0 4fJ  %明の央IIAカ 本発明の一実施例を帛4図を用いて詳述する。
(dJ Purpose of the Invention The invention is not based on the above drawbacks of the conventional art. The purpose is to provide a vertical turret pressure IG1 with a rectifier diode and a transistor and a rectifier M14i1 with two transformers and a transducer. - A flat Il# circuit consisting of an inductance and a capacitor [with an output voltage of 19 and an on-state threshold t of the transistor
''In the constant voltage lP!l path that supplies a constant voltage to the load, the slope output voltage is compared with a predetermined reference voltage, and JJ
II- Comparison of the broom 1 to be outputted as amplification, increase in the ratio of the hand plate and the sl, and the output of the hand beast and the winding-section pressure of the cough transformer. When the xDsa transistor is turned on at the output of the ratio #Rjw-hand beast and the second ratio #Rjw-hand beast, darkness kI! I+! The number of beasts to be determined is 0.4 fJ %, which is defined as t threat value.One embodiment of the present invention will be described in detail with reference to Fig. 4.

4も凶は不発−の廻電tItI&!l略の一榔成例を示
す図である0図において、第1図と同−査号及び同一記
号のものは、同一のMill箇次は票子倉表わし7は電
圧検出回路、8はパルス幅側岬圓略、9及び10は差動
増−器である。
4 is also a misfire - no Kaiden tItI&! In Figure 0, which is a diagram showing an example of one omitted construction, the same signs and symbols as in Figure 1 are the same Mill numbers, 7 is the voltage detection circuit, and 8 is the pulse width. 9 and 10 are differential amplifiers.

パルス幅側f14LgJ路8からトランジスタ見のベー
スに電圧が加わってトランジス−Qはオンとなり、トラ
ンスTlの一次* m N z −Ns K1L流がp
H,lt’Lることによル、電圧か発生し、この電圧が
二久巷#Ns及びN4に鱒起されて、これによシダイオ
ード1)為及び平滑圏路畠を介して負荷RLK電圧かi
KIMされ、tたダイオードD、、抵恍B1及びコンデ
ンサC3を介して抵抗R,に電圧がig給される01<
 /L/ J 幅側#回路8からトランジスタQのベー
スに電圧が加わらなくなると、トランスTl電圧は反転
し、ダイオードD、・D4はオフとなる。しかし、トラ
ンジスタQかオンの時に平#1路1で1起される電圧が
平滑されているので、トランジスタQがオフとなりても
負□荷KLには電圧か供線6れる0ま友、二次II!!
llllN4に嶽続されている盗仇a烏にも、トランジ
スタQがオンの時に二次舎−84にta起される電圧が
ダイオードD、参抵抗R1及びコンダンTO,によ〕平
均1!されていゐので電圧が供給される◎ 次にこの定電圧回路の制御系のルー1についてll!明
する。
A voltage is applied to the base of the transistor from the pulse width side f14LgJ path 8, turning on the transistor Q, and the primary * m N z -Ns K1L current of the transformer Tl changes to p
By H, lt'L, a voltage is generated, and this voltage is generated at the second line #Ns and N4, which causes the load RLK to flow through the diode 1) and the smooth circuit. Voltage or i
A voltage is supplied to the resistor R through the resistor B1 and the capacitor C3.
/L/J Width side #When voltage is no longer applied to the base of the transistor Q from the circuit 8, the voltage of the transformer Tl is inverted and the diodes D and D4 are turned off. However, when the transistor Q is on, the voltage generated on the line #1 is smoothed, so even when the transistor Q is off, the voltage on the load KL is still 0,2 Next II! !
In addition, when the transistor Q is on, the voltage generated in the secondary circuit 84 connected to the transistor N4 is 1 on average due to the diode D, the resistor R1, and the capacitor TO. ◎ Next, let's talk about Rule 1 of the control system of this constant voltage circuit! I will clarify.

負NRLK供艙される電圧は電圧検出m路7でE・とを
比較し、その−分を増幅して葺―増幅1IsK出力する
。差―増−@sでは11i11jj41@@IIJから
の電圧と抵抗−に加わ石−電圧を比較し、その差分を増
幅してパルス幅制御−路IK出力するOパルス幅劇#回
路8では差―増暢器9の出力により。
The voltage supplied to the negative NRLK is compared with E in the voltage detection line 7, and the negative voltage is amplified and outputted as an amplified 1IsK. The difference - increase - @s compares the voltage from 11i11jj41@@IIJ with the voltage added to the resistor, and the difference is amplified to output the pulse width control path IK. By the output of the enhancer 9.

トランスTl電圧を加える時間幅を設定するOまた。砲
の実施例として1巻fi4のかわ9に二次%1IkNs
K−起される電圧をiW1様O斑流平滑回路を冷いて差
曽増−@Sに入力してもよい・ただし。
Also sets the time width for applying the transformer Tl voltage. As an example of a gun, 1 volume fi 4 glue 9 secondary % 1 IkNs
K-The generated voltage may be cooled through the iW1-like O patchy flow smoothing circuit and input into the difference-increase-@S.However.

この場合、人カー出力閲のアースが共通となるので電圧
構出1&!1jll?k141諭し、入カー出力I!A
嫌用のホトカップ2等を−の箇所に入れる必豐がある0
また本発明は第111に示す定電圧−路に@らずインダ
クタンス及びコンデンナを含む平滑1路を持つ回路で、
負荷に供給される電圧に1ル、トランジスタのオン及び
オフ時間を設定するものであれに、適用できるものであ
る◎ −発1I11の効果 以上Sa明したように%本発明は二次遅れ要素をもつフ
ィードバック系0qPK二久遅れ要素を含まないフィー
ドバック系、すなわち−久迦れ要素をもうフィードバッ
ク系を設けたものである@すなわち、−久遅れ要素t%
つフィードバック系は、不安定な状jlKなることはな
く利得を^(することができるので二次遅れ要素をもつ
フィードバック系の利得が低くても、−次遅れ要素をも
つフィードバック系で利得を高くすることにより、&g
l路全体の利得t−^くすることがで龜る◎よりて不発
@によれば=IjC連れt!素をもりフィードバック系
で十分な位相余裕λび利得余裕を得て安定度を向上させ
、−次遅れ要素を1つフィードバック系で利得を^(す
ることによハ応答速度の速い定電圧回路を提供すること
ができるという効果が得られる。
In this case, the ground for the human car output terminal is common, so voltage configuration 1&! 1jll? k141 admonition, input car output I! A
It is necessary to put the unwanted hot cup 2 etc. in the - place0
Further, the present invention is a circuit having a smoothing path including an inductance and a capacitor instead of a constant voltage path shown in No. 111,
It can be applied to anything that sets the voltage supplied to the load and the on and off times of a transistor.As explained above, the present invention has a second-order delay element. Feedback system with 0qPK A feedback system that does not include a two-time delay element, that is, a feedback system with a -long delay element.
A feedback system with two lag elements can increase its gain without becoming unstable, so even if the gain of a feedback system with a second-order lag element is low, the gain of a feedback system with a -th-order lag element can be increased. By doing &g
According to @, it is faster to increase the overall gain t-^◎=IjC with t! By using the feedback system to improve stability by obtaining sufficient phase margin λ and gain margin, and increasing the gain by using the feedback system with one -order lag element, we can create a constant voltage circuit with a fast response speed. The effect is that it can be provided.

また、−久遅れ要素14つフィードバック系で判侍を薦
くすることによル、回路全体の利得も高くなるので、倣
少な@ルも見逃さすに訂正しようと努めることになり、
ett*も向上するという効果も得ることかで雅る〇
In addition, by recommending Samurai in a feedback system with 14 long-delay elements, the gain of the entire circuit will increase, so we will try to correct even the weakest feedback, without overlooking it.
I am happy that I can also get the effect of improving ett*.

【図面の簡単な説明】[Brief explanation of drawings]

ig1図は従来の定電圧回路の一一威IFIを示す図。 @m図は従来の定電圧回路のボードIIIII%纂S図
は従来の定電圧回路の他の一儒成ガ倉示すaコ第4図は
本発明の定電圧回路の一儒成例を示す図である〇 図中、Eは入力電掘、11・は4準電圧、D!乃至D4
はダイオード%Tlはトランス、Qはトiンジスタ、C
五及びCsはコンデンサ、R1及び凰1は抵抗、Lはイ
ンダクタンス、8sは負荷、1 、 I及び8拡パルス
−11tlllill崗路、畠は平a關路s II m
 6 a 9及び等 1 図 等 ? 困 茅 3 図 第 Φ 回
Figure ig1 is a diagram showing the IFI of a conventional constant voltage circuit. Figure 4 shows an example of the construction of the constant voltage circuit of the present invention. In the figure, E is the input electric current, 11. is the 4 quasi-voltage, and D! ~D4
is a diode, %Tl is a transformer, Q is a transistor, C
5 and Cs are capacitors, R1 and 1 are resistors, L is inductance, 8s is load, 1, I and 8 are expanded pulses - 11tlllill gang road, Hatake is flat akan road s II m
6 a 9 and etc. 1 Figure etc.? Trouble 3 Figure No. Φ

Claims (1)

【特許請求の範囲】 トランス及び該トランスの1久411111mにトラン
7スタ及び該トランスの二次*si匈に葺扼ダイオード
、インダクタンス、コンデンサからなる平滑1g1錯t
もち一田力電圧にシシ、該トランジスタのオン時間を設
定して負荷に定電圧【供給する定電圧Al11J略にお
いて、IX出力電圧と所足の基準電圧とt比較し、jI
11輪して出力する塵lの比叡増暢手歇及び該第1の比
幀増−手板の田方と砿トランスのI?!!巌電圧全電圧
平拘化した電圧とを比較し、増嘱して出力する扇4の比
叡JIIIlli&手駿及び鍍墨3の比&増幅+威の出
力KLシ、威トランジスタのオン#闇に設定する手段を
設けたことt物像とする定電圧&&!l路。
[Claims] A smoothing 1g1 complex consisting of a transformer, a transformer 7 stars in the first 411111m of the transformer, and a shunt diode, an inductance, and a capacitor in the secondary *si* of the transformer.
Set the on-time of the transistor to the voltage, set the on-time of the transistor, and apply a constant voltage to the load.
11 wheels and output dust l Hiei Masunobu handshake and the first Hihei Masanobu handboard Tagata and I? ! ! Compare the Iwao voltage with the flattened voltage and increase the output. Ratio of Ougi 4's Hiei JIIIlli & Teshun and Kasumi 3 & amplification + I output KL, I set transistor on #dark. A constant voltage to make the object image &&! l road.
JP20428581A 1981-12-17 1981-12-17 Constant voltage circuit Pending JPS58105312A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20428581A JPS58105312A (en) 1981-12-17 1981-12-17 Constant voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20428581A JPS58105312A (en) 1981-12-17 1981-12-17 Constant voltage circuit

Publications (1)

Publication Number Publication Date
JPS58105312A true JPS58105312A (en) 1983-06-23

Family

ID=16487944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20428581A Pending JPS58105312A (en) 1981-12-17 1981-12-17 Constant voltage circuit

Country Status (1)

Country Link
JP (1) JPS58105312A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285368A (en) * 1991-02-28 1994-02-08 Canon Kabushiki Kaisha Power source device responsive to supplemental plural output voltages
WO1997033360A1 (en) * 1996-03-08 1997-09-12 Siemens Aktiengesellschaft Circuit arrangement for stabilising the control response of directly controlled converters

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285368A (en) * 1991-02-28 1994-02-08 Canon Kabushiki Kaisha Power source device responsive to supplemental plural output voltages
WO1997033360A1 (en) * 1996-03-08 1997-09-12 Siemens Aktiengesellschaft Circuit arrangement for stabilising the control response of directly controlled converters

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