JPS5759457U - - Google Patents

Info

Publication number
JPS5759457U
JPS5759457U JP1980136418U JP13641880U JPS5759457U JP S5759457 U JPS5759457 U JP S5759457U JP 1980136418 U JP1980136418 U JP 1980136418U JP 13641880 U JP13641880 U JP 13641880U JP S5759457 U JPS5759457 U JP S5759457U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1980136418U
Other languages
Japanese (ja)
Other versions
JPS6138193Y2 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1980136418U priority Critical patent/JPS6138193Y2/ja
Publication of JPS5759457U publication Critical patent/JPS5759457U/ja
Application granted granted Critical
Publication of JPS6138193Y2 publication Critical patent/JPS6138193Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP1980136418U 1980-09-25 1980-09-25 Expired JPS6138193Y2 (https=)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980136418U JPS6138193Y2 (https=) 1980-09-25 1980-09-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980136418U JPS6138193Y2 (https=) 1980-09-25 1980-09-25

Publications (2)

Publication Number Publication Date
JPS5759457U true JPS5759457U (https=) 1982-04-08
JPS6138193Y2 JPS6138193Y2 (https=) 1986-11-05

Family

ID=29496532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980136418U Expired JPS6138193Y2 (https=) 1980-09-25 1980-09-25

Country Status (1)

Country Link
JP (1) JPS6138193Y2 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4893303B2 (ja) * 2006-12-29 2012-03-07 株式会社デンソー 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53133571U (https=) * 1977-03-29 1978-10-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53133571U (https=) * 1977-03-29 1978-10-23

Also Published As

Publication number Publication date
JPS6138193Y2 (https=) 1986-11-05

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