JPS5745624A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5745624A
JPS5745624A JP55121523A JP12152380A JPS5745624A JP S5745624 A JPS5745624 A JP S5745624A JP 55121523 A JP55121523 A JP 55121523A JP 12152380 A JP12152380 A JP 12152380A JP S5745624 A JPS5745624 A JP S5745624A
Authority
JP
Japan
Prior art keywords
line
information
signal lines
spare
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55121523A
Other languages
Japanese (ja)
Inventor
Takashi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55121523A priority Critical patent/JPS5745624A/en
Publication of JPS5745624A publication Critical patent/JPS5745624A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Abstract

PURPOSE:To enable transfer even at the production of failure and to detect failed position, by transferring the position of failed line at a ring shift circuit to a spare position, even if one information line is in failure, through the provision of a spare line in addition to an information line on a common bus. CONSTITUTION:A spare line 1b is provided on a common bus 1 consisting of several information lines (e.g., 4 lines)1a. Normally, a bus receiver 4 receives information, signal lines 100-103 are transmitted to internal signal lines 500-503 respectively and transmitted to a logical circuit 8. Similarly, the information from the logical circuit is given to the information lines via internal signal lines 300-303 and signal lines 400-403. If one information line is in failure, this is detected at a bus failure detecting circuit, and the connection between the signal lines and the internal signal lines 300-304 is switched with ring shift circuits 6, 7 and it is transferred to a spare line 1b with a spare signal line 1b.
JP55121523A 1980-09-02 1980-09-02 Information processor Pending JPS5745624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55121523A JPS5745624A (en) 1980-09-02 1980-09-02 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55121523A JPS5745624A (en) 1980-09-02 1980-09-02 Information processor

Publications (1)

Publication Number Publication Date
JPS5745624A true JPS5745624A (en) 1982-03-15

Family

ID=14813328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55121523A Pending JPS5745624A (en) 1980-09-02 1980-09-02 Information processor

Country Status (1)

Country Link
JP (1) JPS5745624A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574718A (en) * 1994-07-01 1996-11-12 Dsc Communications Corporation Signal protection and monitoring system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574718A (en) * 1994-07-01 1996-11-12 Dsc Communications Corporation Signal protection and monitoring system

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