JPS57210664A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS57210664A
JPS57210664A JP56095809A JP9580981A JPS57210664A JP S57210664 A JPS57210664 A JP S57210664A JP 56095809 A JP56095809 A JP 56095809A JP 9580981 A JP9580981 A JP 9580981A JP S57210664 A JPS57210664 A JP S57210664A
Authority
JP
Japan
Prior art keywords
memory cell
transistor
source
ground
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56095809A
Other languages
Japanese (ja)
Other versions
JPS611901B2 (en
Inventor
Hiroshi Shinohara
Kenji Anami
Masahiko Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56095809A priority Critical patent/JPS57210664A/en
Publication of JPS57210664A publication Critical patent/JPS57210664A/en
Publication of JPS611901B2 publication Critical patent/JPS611901B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Abstract

PURPOSE:To reduce the size of a chip in a static memory by reducing the number of ground lines per one memory cell. CONSTITUTION:A static semiconductor memory cell having transfer transistors Q1, Q2, drive transistors Q3, Q4, load resistors R1, R2 made of high resistance polysilicon layers, a word line 3-1, a power wire 3-2, complimentary bit wires 4-1, 4-2, and a ground wire 4-3 is obtained. In this case, a common active region 7 commonly using the source of a transistor Q4 of n-th memory cell and the source of a transistor Q3L of (n-1)-th memory cell, and a common active region 8 commonly using the source of the transistor Q3 of the n-th memory cell and the source of an (n+1)-th transistor Q4R are formed, and the regions 7, 8 are connected via contacts 9, 10 to the metal wire 4-3 of the ground wire. In this manner, the ground wires per one bit can be set in average to 0.5.
JP56095809A 1981-06-19 1981-06-19 Semiconductor memory device Granted JPS57210664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56095809A JPS57210664A (en) 1981-06-19 1981-06-19 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56095809A JPS57210664A (en) 1981-06-19 1981-06-19 Semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS57210664A true JPS57210664A (en) 1982-12-24
JPS611901B2 JPS611901B2 (en) 1986-01-21

Family

ID=14147746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56095809A Granted JPS57210664A (en) 1981-06-19 1981-06-19 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS57210664A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315146A (en) * 1992-03-19 1994-05-24 Fujitsu Limited Semiconductor memory device having specific layout configuration of n-MOS memory cells
US5541427A (en) * 1993-12-03 1996-07-30 International Business Machines Corporation SRAM cell with capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315146A (en) * 1992-03-19 1994-05-24 Fujitsu Limited Semiconductor memory device having specific layout configuration of n-MOS memory cells
US5541427A (en) * 1993-12-03 1996-07-30 International Business Machines Corporation SRAM cell with capacitor

Also Published As

Publication number Publication date
JPS611901B2 (en) 1986-01-21

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