JPS57195375A - Channel controller - Google Patents
Channel controllerInfo
- Publication number
- JPS57195375A JPS57195375A JP56080257A JP8025781A JPS57195375A JP S57195375 A JPS57195375 A JP S57195375A JP 56080257 A JP56080257 A JP 56080257A JP 8025781 A JP8025781 A JP 8025781A JP S57195375 A JPS57195375 A JP S57195375A
- Authority
- JP
- Japan
- Prior art keywords
- address
- cash
- stack
- store request
- bias4
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To minimize a decrease in the execution speed of a CPU, by storing a buffer invalidating address stack with an address to be searched only once for the same block address in a channel control part connected to CASH. CONSTITUTION:On the start of storing operation, a store request flag STRQ6 is set, and in response to it, a CPU2 sends a store request to a main memory MMU1. The address accompaying the store request is stacked in a buffer invalidating address stack BIAS4. According to the stacked address, a cash directory AA3 is searched and the cash block in the address, when effective, is made ineffective. In a buffer invalidating request flag BIRQ12, the output logic value of an LU11 is set at the timing with which a CHC5 accesses a main storage part 1. Only when a byte address BA10 has a specific bit pattern, the current address is stored in the stack BIAS4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56080257A JPS57195375A (en) | 1981-05-27 | 1981-05-27 | Channel controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56080257A JPS57195375A (en) | 1981-05-27 | 1981-05-27 | Channel controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57195375A true JPS57195375A (en) | 1982-12-01 |
Family
ID=13713256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56080257A Pending JPS57195375A (en) | 1981-05-27 | 1981-05-27 | Channel controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57195375A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61221845A (en) * | 1985-03-05 | 1986-10-02 | Fujitsu Ltd | Producing system for invalidated address of buffer memory |
JPS6215644A (en) * | 1985-07-15 | 1987-01-24 | Nec Corp | Cache memory control circuit |
JPH0659974A (en) * | 1992-07-02 | 1994-03-04 | Internatl Business Mach Corp <Ibm> | Computer system |
JP2005209163A (en) * | 2003-12-22 | 2005-08-04 | Matsushita Electric Ind Co Ltd | Memory system control method |
JP2009282920A (en) * | 2008-05-26 | 2009-12-03 | Toshiba Corp | Cache memory device |
-
1981
- 1981-05-27 JP JP56080257A patent/JPS57195375A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61221845A (en) * | 1985-03-05 | 1986-10-02 | Fujitsu Ltd | Producing system for invalidated address of buffer memory |
JPS6215644A (en) * | 1985-07-15 | 1987-01-24 | Nec Corp | Cache memory control circuit |
JPH058459B2 (en) * | 1985-07-15 | 1993-02-02 | Nippon Electric Co | |
JPH0659974A (en) * | 1992-07-02 | 1994-03-04 | Internatl Business Mach Corp <Ibm> | Computer system |
JP2005209163A (en) * | 2003-12-22 | 2005-08-04 | Matsushita Electric Ind Co Ltd | Memory system control method |
JP2009282920A (en) * | 2008-05-26 | 2009-12-03 | Toshiba Corp | Cache memory device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0198231A3 (en) | Data processor with parallel instruction control and execution | |
JPS57185545A (en) | Information processor | |
JPS57195375A (en) | Channel controller | |
JPS5680872A (en) | Buffer memory control system | |
JPS56169281A (en) | Data processor | |
JPS5730170A (en) | Buffer memory control system | |
JPS5534314A (en) | Key memory system | |
JPS57153356A (en) | Auxiliary storage controller | |
JPS55154623A (en) | Input and output control system | |
JPS54128639A (en) | Control system for cash memory | |
JPS5593580A (en) | Buffer memory control system | |
JPS5562576A (en) | Information processing unit with address conversion function | |
JPS526032A (en) | Main storage control unit | |
JPS5523555A (en) | Micro cash system having resident bit | |
JPS5533252A (en) | Memory system | |
JPS5475231A (en) | Buffer memory control system | |
JPS5577072A (en) | Buffer memory control system | |
FR2298139A1 (en) | Data processing system with fast access auxiliary programme store - has programme store coupled to large capacity buffer controlled in groups over gating circuit | |
JPS5696334A (en) | Prefetch system | |
JPS5819784A (en) | Storage device | |
JPS57212678A (en) | Buffer storage device | |
JPS57138077A (en) | Variable length string buffer device | |
JPS564843A (en) | Address conversion system | |
JPS55102053A (en) | Address comparison circuit | |
JPS57199060A (en) | Address controlling device |