JPS57194618A - Digital filter circuit - Google Patents

Digital filter circuit

Info

Publication number
JPS57194618A
JPS57194618A JP8026081A JP8026081A JPS57194618A JP S57194618 A JPS57194618 A JP S57194618A JP 8026081 A JP8026081 A JP 8026081A JP 8026081 A JP8026081 A JP 8026081A JP S57194618 A JPS57194618 A JP S57194618A
Authority
JP
Japan
Prior art keywords
input data
absolute value
value
maximum variation
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8026081A
Other languages
Japanese (ja)
Inventor
Hiroshi Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8026081A priority Critical patent/JPS57194618A/en
Publication of JPS57194618A publication Critical patent/JPS57194618A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks

Abstract

PURPOSE:To use the titled circuit also as a circuit where variable data are inputted, by setting the maximum variation permissible value of input data stored in a memory to an optimum value. CONSTITUTION:Input data 1 is inputted through a receiver 2. At the same time, last input data 4 is read out of a buffer memory 3. This is inputted to a subtracter 8 to calculate the difference from the current input data 1. This difference is converted into an absolute value 10 by an absolute value circuit 9. This absolute value is compared by a comparator 12 with the maximum variation permissible value of the input data stored in a memory 11 and when the absolute value 10 of the difference between the 1st input data and current input data is less than the maximum variation permissible value, a gate 6 is opened to store the current input data 1 as real data in a main memory 7. When the absolute value 10 is greater than the maximum variation permissible value, the gate 6 is closed and the current input data 1 is not stored in the main memory 7.
JP8026081A 1981-05-27 1981-05-27 Digital filter circuit Pending JPS57194618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8026081A JPS57194618A (en) 1981-05-27 1981-05-27 Digital filter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8026081A JPS57194618A (en) 1981-05-27 1981-05-27 Digital filter circuit

Publications (1)

Publication Number Publication Date
JPS57194618A true JPS57194618A (en) 1982-11-30

Family

ID=13713338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8026081A Pending JPS57194618A (en) 1981-05-27 1981-05-27 Digital filter circuit

Country Status (1)

Country Link
JP (1) JPS57194618A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5123663U (en) * 1974-08-12 1976-02-21
JPS5141933A (en) * 1974-08-08 1976-04-08 Teldix Gmbh

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5141933A (en) * 1974-08-08 1976-04-08 Teldix Gmbh
JPS5123663U (en) * 1974-08-12 1976-02-21

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