JPS57187748A - Branch instruction execution system - Google Patents

Branch instruction execution system

Info

Publication number
JPS57187748A
JPS57187748A JP7146781A JP7146781A JPS57187748A JP S57187748 A JPS57187748 A JP S57187748A JP 7146781 A JP7146781 A JP 7146781A JP 7146781 A JP7146781 A JP 7146781A JP S57187748 A JPS57187748 A JP S57187748A
Authority
JP
Japan
Prior art keywords
branch
instruction
circuit
inputted
continuous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7146781A
Other languages
Japanese (ja)
Inventor
Kozo Yamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7146781A priority Critical patent/JPS57187748A/en
Publication of JPS57187748A publication Critical patent/JPS57187748A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To shorten the time equired for the execution of a branch instruction, by setting an instruction of an objective branch destination out of plural branch destinations to an instruction register. CONSTITUTION:The instruction code of an instruction stored in upper 4 bytes of an instruction register 14 and the instruction code of an instruction stoerd in lower 4 bytes are inputted to a branch continuous discriminating circuit 18 to detect the continuity of read branch instructions. Branch condition flags (a) and (b) of continuous branch instructions A and B are inputted to a branch destination discriminating circuit 19 and are compared with condition code information to discriminate a branch destination. The output of the circuit 18 and the output of the circuit 19 are inputted to a continuous branch controlling circuit 20 to perform the control for fetching of the instruction of the branch destination. Thus, the instruction of the objective branch destination out of plural branch destinations is set to the instruction register 14.
JP7146781A 1981-05-14 1981-05-14 Branch instruction execution system Pending JPS57187748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7146781A JPS57187748A (en) 1981-05-14 1981-05-14 Branch instruction execution system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7146781A JPS57187748A (en) 1981-05-14 1981-05-14 Branch instruction execution system

Publications (1)

Publication Number Publication Date
JPS57187748A true JPS57187748A (en) 1982-11-18

Family

ID=13461424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7146781A Pending JPS57187748A (en) 1981-05-14 1981-05-14 Branch instruction execution system

Country Status (1)

Country Link
JP (1) JPS57187748A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158442A (en) * 1983-03-01 1984-09-07 Hitachi Ltd Instruction read control system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121449A (en) * 1973-03-19 1974-11-20
JPS5048853A (en) * 1973-09-03 1975-05-01

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121449A (en) * 1973-03-19 1974-11-20
JPS5048853A (en) * 1973-09-03 1975-05-01

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158442A (en) * 1983-03-01 1984-09-07 Hitachi Ltd Instruction read control system
JPH0472253B2 (en) * 1983-03-01 1992-11-17 Hitachi Ltd

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