JPS57179984A - Two dimension address storage device - Google Patents

Two dimension address storage device

Info

Publication number
JPS57179984A
JPS57179984A JP6216981A JP6216981A JPS57179984A JP S57179984 A JPS57179984 A JP S57179984A JP 6216981 A JP6216981 A JP 6216981A JP 6216981 A JP6216981 A JP 6216981A JP S57179984 A JPS57179984 A JP S57179984A
Authority
JP
Japan
Prior art keywords
address
storage capacity
connection cable
memory
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6216981A
Other languages
Japanese (ja)
Inventor
Keiji Nagato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6216981A priority Critical patent/JPS57179984A/en
Publication of JPS57179984A publication Critical patent/JPS57179984A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To achieve arbitrary wiring change between an address register and a memory chip accompanied with the change in a storage capacity, by using an address connection cable in wiring state corresponding to the storage capacity in advance. CONSTITUTION:An address connection cable 8 is internally wired in advance so that each bit of address designation information is assigned to an address decoder 5 according to the storage capacity of a memory board 1, i.e., the number of memory chips 4. Address information 8 is freely removably to an output pin 6 and an input pin 7, and thus, no change for the hardware is required by preparing a plurality of wiring states according to the storage capacity. A memory controller 2 and the memory board 1 are connected with a connection cable 9 and output information of the address decoder 5 is given to the memory board 1 via this connection cable 9.
JP6216981A 1981-04-24 1981-04-24 Two dimension address storage device Pending JPS57179984A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6216981A JPS57179984A (en) 1981-04-24 1981-04-24 Two dimension address storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6216981A JPS57179984A (en) 1981-04-24 1981-04-24 Two dimension address storage device

Publications (1)

Publication Number Publication Date
JPS57179984A true JPS57179984A (en) 1982-11-05

Family

ID=13192348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6216981A Pending JPS57179984A (en) 1981-04-24 1981-04-24 Two dimension address storage device

Country Status (1)

Country Link
JP (1) JPS57179984A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400293A (en) * 1992-11-10 1995-03-21 Oki Electric Industry Co., Ltd. Method of setting addresses of memories

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400293A (en) * 1992-11-10 1995-03-21 Oki Electric Industry Co., Ltd. Method of setting addresses of memories

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