JPS57172587A - Voltage boosting circuit of memory circuit - Google Patents

Voltage boosting circuit of memory circuit

Info

Publication number
JPS57172587A
JPS57172587A JP56057142A JP5714281A JPS57172587A JP S57172587 A JPS57172587 A JP S57172587A JP 56057142 A JP56057142 A JP 56057142A JP 5714281 A JP5714281 A JP 5714281A JP S57172587 A JPS57172587 A JP S57172587A
Authority
JP
Japan
Prior art keywords
vcc
voltage
word line
signal
phia
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56057142A
Other languages
Japanese (ja)
Inventor
Jun Eto
Yoshiki Kawajiri
Ryoichi Hori
Kiyoo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56057142A priority Critical patent/JPS57172587A/en
Priority to US06/358,678 priority patent/US4503522A/en
Priority to EP82301347A priority patent/EP0061289B1/en
Priority to DE8282301347T priority patent/DE3278833D1/en
Publication of JPS57172587A publication Critical patent/JPS57172587A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Abstract

PURPOSE:To achieve sufficient writing operation by boosting the voltage of a word line by capacitances >=2 times. CONSTITUTION:Switches SW1, SW2, and SW3 are all in on states initially, and switches SW1 and SW3 are turned off; and then a signal phiA generated by a generating circuit 40 goes up to a level Vcc, and consequently the potential of a word line W is raised to the Vcc. A signal phiB goes up to a high level (Vcc) and is passed through a capacitance CB to boost the voltage of the word line W above the Vcc. At this time, the voltage phiA at the output terminal of the phiA generating circuit is also boosted. Then, the switch SW2 is turned off and a signal phiC goes up to the high level (Vcc). The signal phiC further boosts the voltage of the word line W through a capacitance Cc.
JP56057142A 1981-03-17 1981-04-17 Voltage boosting circuit of memory circuit Pending JPS57172587A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56057142A JPS57172587A (en) 1981-04-17 1981-04-17 Voltage boosting circuit of memory circuit
US06/358,678 US4503522A (en) 1981-03-17 1982-03-16 Dynamic type semiconductor monolithic memory
EP82301347A EP0061289B1 (en) 1981-03-17 1982-03-16 Dynamic type semiconductor monolithic memory
DE8282301347T DE3278833D1 (en) 1981-03-17 1982-03-16 Dynamic type semiconductor monolithic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56057142A JPS57172587A (en) 1981-04-17 1981-04-17 Voltage boosting circuit of memory circuit

Publications (1)

Publication Number Publication Date
JPS57172587A true JPS57172587A (en) 1982-10-23

Family

ID=13047317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56057142A Pending JPS57172587A (en) 1981-03-17 1981-04-17 Voltage boosting circuit of memory circuit

Country Status (1)

Country Link
JP (1) JPS57172587A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377138A (en) * 1990-01-24 1994-12-27 Seiko Epson Corporation Semiconductor memory and data processing device
US5526319A (en) * 1995-01-31 1996-06-11 International Business Machines Corporation Memory with adiabatically switched bit lines
US6125075A (en) * 1985-07-22 2000-09-26 Hitachi, Ltd. Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6125075A (en) * 1985-07-22 2000-09-26 Hitachi, Ltd. Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
US6363029B1 (en) 1985-07-22 2002-03-26 Hitachi, Ltd. Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
US6970391B2 (en) 1985-07-22 2005-11-29 Renesas Technology Corporation Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
US7002856B2 (en) 1986-07-18 2006-02-21 Renesas Technology Corporation Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
US5377138A (en) * 1990-01-24 1994-12-27 Seiko Epson Corporation Semiconductor memory and data processing device
US5526319A (en) * 1995-01-31 1996-06-11 International Business Machines Corporation Memory with adiabatically switched bit lines

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