JPS5717161A - Method of producing mos and bipolar semiconductor integrated circuits - Google Patents
Method of producing mos and bipolar semiconductor integrated circuitsInfo
- Publication number
- JPS5717161A JPS5717161A JP7285381A JP7285381A JPS5717161A JP S5717161 A JPS5717161 A JP S5717161A JP 7285381 A JP7285381 A JP 7285381A JP 7285381 A JP7285381 A JP 7285381A JP S5717161 A JPS5717161 A JP S5717161A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuits
- semiconductor integrated
- bipolar semiconductor
- producing mos
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W15/00—Highly-doped buried regions of integrated devices
- H10W15/01—Manufacture or treatment
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19803018848 DE3018848A1 (de) | 1980-05-16 | 1980-05-16 | Verfahren zur herstellung monolithisch intetgrierter mos- und bipolar-halbleiteranordnungen fuer den vhf- und den uhf-bereich |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5717161A true JPS5717161A (en) | 1982-01-28 |
| JPH0235469B2 JPH0235469B2 (https=) | 1990-08-10 |
Family
ID=6102649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7285381A Granted JPS5717161A (en) | 1980-05-16 | 1981-05-14 | Method of producing mos and bipolar semiconductor integrated circuits |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5717161A (https=) |
| DE (1) | DE3018848A1 (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01155653A (ja) * | 1987-11-13 | 1989-06-19 | Texas Instr Inc <Ti> | 高電圧併合バイポーラ/cmos集積回路 |
| JPH01226172A (ja) * | 1988-03-07 | 1989-09-08 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置とその製造方法 |
| JPH02130868A (ja) * | 1988-11-10 | 1990-05-18 | Toshiba Corp | 半導体装置 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4411869C2 (de) * | 1994-04-06 | 1997-05-15 | Siemens Ag | Schaltungsanordnung mit einer integrierten Treiberschaltungsanordnung |
-
1980
- 1980-05-16 DE DE19803018848 patent/DE3018848A1/de active Granted
-
1981
- 1981-05-14 JP JP7285381A patent/JPS5717161A/ja active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01155653A (ja) * | 1987-11-13 | 1989-06-19 | Texas Instr Inc <Ti> | 高電圧併合バイポーラ/cmos集積回路 |
| JPH01226172A (ja) * | 1988-03-07 | 1989-09-08 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置とその製造方法 |
| JPH02130868A (ja) * | 1988-11-10 | 1990-05-18 | Toshiba Corp | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3018848C2 (https=) | 1989-02-16 |
| JPH0235469B2 (https=) | 1990-08-10 |
| DE3018848A1 (de) | 1981-11-26 |
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