JPS57145476A - 2-dimensional recorder - Google Patents
2-dimensional recorderInfo
- Publication number
- JPS57145476A JPS57145476A JP3066881A JP3066881A JPS57145476A JP S57145476 A JPS57145476 A JP S57145476A JP 3066881 A JP3066881 A JP 3066881A JP 3066881 A JP3066881 A JP 3066881A JP S57145476 A JPS57145476 A JP S57145476A
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- line
- dots
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/40068—Modification of image resolution, i.e. determining the values of picture elements at new relative positions
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Editing Of Facsimile Originals (AREA)
- Facsimile Heads (AREA)
Abstract
PURPOSE:To distribute all dots into a reticulate form, by calculating and recording the interpolating data to plural dots which are recorded in adjacent to each other in an input data. CONSTITUTION:An input data A is supplied to a data input terminal 12 for printing. In this case, a 1-line data is equal to a time-division data which has a time slot accoring to dots (k) equivalent at least to a line. Such input data B is supplied to a time axis compressing circuit 22 to be compressed down to 1/2. This compressed data C is fed to an adder circuit 23, a 1-dot delaying circuit 24, a 1-line delaying circuit 25 and a 1/2-line delaying circuit 26 respectively to obtain data D, E and F. The circuit 23 adds the data C, D, E and F together and then compresses the added data down to 1/4 to calculate an interpolating data in the form of a mean value of each data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3066881A JPS57145476A (en) | 1981-03-04 | 1981-03-04 | 2-dimensional recorder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3066881A JPS57145476A (en) | 1981-03-04 | 1981-03-04 | 2-dimensional recorder |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57145476A true JPS57145476A (en) | 1982-09-08 |
Family
ID=12310108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3066881A Pending JPS57145476A (en) | 1981-03-04 | 1981-03-04 | 2-dimensional recorder |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57145476A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5135215A (en) * | 1974-09-20 | 1976-03-25 | Tokyo Shibaura Electric Co | |
JPS5157448A (en) * | 1974-11-15 | 1976-05-19 | Hitachi Electronics | |
JPS53138630A (en) * | 1977-05-10 | 1978-12-04 | Ricoh Co Ltd | Picture processing method |
JPS5451311A (en) * | 1977-09-29 | 1979-04-23 | Toshiba Corp | Facsmile terminal equipment for fine picture |
-
1981
- 1981-03-04 JP JP3066881A patent/JPS57145476A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5135215A (en) * | 1974-09-20 | 1976-03-25 | Tokyo Shibaura Electric Co | |
JPS5157448A (en) * | 1974-11-15 | 1976-05-19 | Hitachi Electronics | |
JPS53138630A (en) * | 1977-05-10 | 1978-12-04 | Ricoh Co Ltd | Picture processing method |
JPS5451311A (en) * | 1977-09-29 | 1979-04-23 | Toshiba Corp | Facsmile terminal equipment for fine picture |
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