JPS57128077A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS57128077A
JPS57128077A JP1276881A JP1276881A JPS57128077A JP S57128077 A JPS57128077 A JP S57128077A JP 1276881 A JP1276881 A JP 1276881A JP 1276881 A JP1276881 A JP 1276881A JP S57128077 A JPS57128077 A JP S57128077A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
layer
performing
formed
aperture
schottky barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1276881A
Inventor
Atsuhiko Menju
Shinji Saito
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Abstract

PURPOSE:To simplify manufacture of the semiconductor device provided with a Schottky barrier by a method wherein a guard ring secion is provided at a Schottky barrier section by performing self-alignment, and a highly integrated Schottky barrier diode is formed. CONSTITUTION:A thermal oxide film 12 is fromed on an N type silicon substrate 11 by performing thermal oxidation and an aperture 13 is provided at the expected part whereon the Schottky barrier will be formed by performing a selective etching on the film 12. Then, p type impurity boron-added polycrystalline silicon layer 14 of prescribed thickness is deposited on the film 12 including the aperture 13, a reactive ion etching is then performed on the layer 14 from the surface to the lower part, and an annular residual polycrystalline silicon layer 14' is remained at the inner circumferential part of the aperture 13. Then, boron is diffused from the layer 14' to the substrate 11 by performing heat treatment, and an annular P<+> type guard reing layer 15 is formed on the aperture 13 by performing self-alignment. Then, after a silicide layer 16 has been formed on the surface of the layer 14' which was exposed by the heat treatment, an Al wiring 17 is formed by performing a patterning.
JP1276881A 1981-01-30 1981-01-30 Semiconductor device and manufacture thereof Pending JPS57128077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1276881A JPS57128077A (en) 1981-01-30 1981-01-30 Semiconductor device and manufacture thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1276881A JPS57128077A (en) 1981-01-30 1981-01-30 Semiconductor device and manufacture thereof
US06341588 US4414737A (en) 1981-01-30 1982-01-21 Production of Schottky barrier diode
DE19823202608 DE3202608C2 (en) 1981-01-30 1982-01-27

Publications (1)

Publication Number Publication Date
JPS57128077A true true JPS57128077A (en) 1982-08-09

Family

ID=11814573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1276881A Pending JPS57128077A (en) 1981-01-30 1981-01-30 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57128077A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696025A (en) * 1996-02-02 1997-12-09 Micron Technology, Inc. Method of forming guard ringed schottky diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696025A (en) * 1996-02-02 1997-12-09 Micron Technology, Inc. Method of forming guard ringed schottky diode

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