JPS57112052A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57112052A
JPS57112052A JP18722280A JP18722280A JPS57112052A JP S57112052 A JPS57112052 A JP S57112052A JP 18722280 A JP18722280 A JP 18722280A JP 18722280 A JP18722280 A JP 18722280A JP S57112052 A JPS57112052 A JP S57112052A
Authority
JP
Japan
Prior art keywords
upper layer
layer wiring
wiring
bridge
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18722280A
Other languages
Japanese (ja)
Other versions
JPS6161699B2 (en
Inventor
Masao Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18722280A priority Critical patent/JPS57112052A/en
Publication of JPS57112052A publication Critical patent/JPS57112052A/en
Publication of JPS6161699B2 publication Critical patent/JPS6161699B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To facilitate the removal of a bridge produced at the gap of a multilayer wiring, by providing a projection between regions where a lower layer wiring crosses two upper layer wirings, and photo-etching the upper layer wiring which remains at the end of projection after the formation of upper layer wiring. CONSTITUTION:For instance, a lower layer wiring 4 is formed on a field film 2 of element-formed substrate 1 in a shape that provides a horizontal projection 11 between regions where the wiring 4 is due to cross two upper layer wiring 8. Next, the upper layer wiring 8 is formed via an interlayer film 5, and a resist film 9 is coated. An opening 12 is provided at the end of a bridge 6 formed along the projection 11. Next, the end of bridge 6' is removed after etching evenly with etching material for the upper layer wiring 8. The resist film 9 is removed and the multilayer wiring structure is made. This facilitates removal of the bridge 6' and prevents the upper layer wiring 8 from over-etching. This also improves the yield and reliability of multilayer wiring.
JP18722280A 1980-12-29 1980-12-29 Manufacture of semiconductor device Granted JPS57112052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18722280A JPS57112052A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18722280A JPS57112052A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57112052A true JPS57112052A (en) 1982-07-12
JPS6161699B2 JPS6161699B2 (en) 1986-12-26

Family

ID=16202201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18722280A Granted JPS57112052A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57112052A (en)

Also Published As

Publication number Publication date
JPS6161699B2 (en) 1986-12-26

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