Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/04—Addressing variable-length words or parts of words
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
  • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Memory System Of A Hierarchy Structure (AREA)

Applications Claiming Priority (1)

Publications (2)

Family

ID=23137121

Family Applications (1)

Country Status (6)

Families Citing this family (49)

Family Cites Families (8)

• 1972
  • 1972-10-05 US US00295303A patent/US3800292A/en not_active Expired - Lifetime
• 1973
  • 1973-07-13 CA CA176,385A patent/CA1002204A/en not_active Expired
  • 1973-08-09 GB GB3774173A patent/GB1433393A/en not_active Expired
  • 1973-08-09 JP JP8889873A patent/JPS5710498B2/ja not_active Expired
  • 1973-10-04 FR FR7335438A patent/FR2202611A5/fr not_active Expired
  • 1973-10-05 DE DE19732350225 patent/DE2350225A1/de active Granted

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