JPS5677710A - Zero-point adjusting circuit - Google Patents
Zero-point adjusting circuitInfo
- Publication number
- JPS5677710A JPS5677710A JP15508879A JP15508879A JPS5677710A JP S5677710 A JPS5677710 A JP S5677710A JP 15508879 A JP15508879 A JP 15508879A JP 15508879 A JP15508879 A JP 15508879A JP S5677710 A JPS5677710 A JP S5677710A
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- resistance
- supplied
- operational amplifier
- adjustment voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
- Amplifiers (AREA)
Abstract
PURPOSE: To secure a steady zero-poing adjustment, by supplying the fine adjustment voltage to the inverse input terminal of the operational amplifier receiving the supply of the input signal to the noninverse input terminal and at the same time supplying the rough adjustment voltage to the same terminal via the operational amplifier and the resistance.
CONSTITUTION: The input signal supplied to the input terminal 1 is amplifier through the operational amplifier OP3, and the amplified input signal ei is supplied to the noninverse input terminal of the operational amplifier OP1. The fine adjustment voltage es is divided by the resistances r1 and r2 and then supplied to the inverse input terminal of the amplifier OP1 via the resistance r3, and the resistance r4 is connected between the output terminal 2 and the inverse input terminal. The rough adjustment voltage V is supplied to the inverse input terminal of the OP1 via the OP2 and the resistance R. To increase the gain, the R is reduced with no excessive increment required for r4. With a reduction of R, the overall range of adjustment is increased. As a result, a steady zero-point adjustment becomes possible.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15508879A JPS5677710A (en) | 1979-11-30 | 1979-11-30 | Zero-point adjusting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15508879A JPS5677710A (en) | 1979-11-30 | 1979-11-30 | Zero-point adjusting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5677710A true JPS5677710A (en) | 1981-06-26 |
Family
ID=15598381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15508879A Pending JPS5677710A (en) | 1979-11-30 | 1979-11-30 | Zero-point adjusting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5677710A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60138619A (en) * | 1983-12-27 | 1985-07-23 | Shimadzu Corp | Auto-zero circuit |
JPH01185004A (en) * | 1988-01-19 | 1989-07-24 | Fuji Facom Corp | System for compensating multistage offset |
JP2016225777A (en) * | 2015-05-29 | 2016-12-28 | 日本電信電話株式会社 | Amplitude detection circuit |
JP2016225776A (en) * | 2015-05-29 | 2016-12-28 | 日本電信電話株式会社 | Weighted addition and subtraction circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5481760A (en) * | 1977-12-12 | 1979-06-29 | Nec Corp | Audio amplifier |
-
1979
- 1979-11-30 JP JP15508879A patent/JPS5677710A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5481760A (en) * | 1977-12-12 | 1979-06-29 | Nec Corp | Audio amplifier |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60138619A (en) * | 1983-12-27 | 1985-07-23 | Shimadzu Corp | Auto-zero circuit |
JPH01185004A (en) * | 1988-01-19 | 1989-07-24 | Fuji Facom Corp | System for compensating multistage offset |
JP2016225777A (en) * | 2015-05-29 | 2016-12-28 | 日本電信電話株式会社 | Amplitude detection circuit |
JP2016225776A (en) * | 2015-05-29 | 2016-12-28 | 日本電信電話株式会社 | Weighted addition and subtraction circuit |
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