JPS5638852A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5638852A
JPS5638852A JP11501879A JP11501879A JPS5638852A JP S5638852 A JPS5638852 A JP S5638852A JP 11501879 A JP11501879 A JP 11501879A JP 11501879 A JP11501879 A JP 11501879A JP S5638852 A JPS5638852 A JP S5638852A
Authority
JP
Japan
Prior art keywords
distance
misfet
signal path
semiconductor region
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11501879A
Other languages
Japanese (ja)
Inventor
Minoru Toyoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11501879A priority Critical patent/JPS5638852A/en
Publication of JPS5638852A publication Critical patent/JPS5638852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Abstract

PURPOSE:To prevent the breakdown of the signal path, by setting the distance between the semiconductor region for the signal path and the high-density semiconductor region formed on a semiconductor substrate, so that the distance on the side of an external imput terminal is longer than the distance on the side of inner wirings. CONSTITUTION:On a semiconductor substrate F, are provided a semiconductor layer E for a signal path for connecting an MISFET (not shown in the Figure) and an external input terminal IN and a high-density semiconductor layer G, with the distance being provided from the layer E to protect the MISFET from the eternal excessive input. The distance between the layers E and G is provided in such a way that the distance Lr on the side of the internal input terminal IN is longer than the distance Lp on the MISFET side. It is desirable to set the separating distance so that it is proportional to the potential drop in the semiconductor region F and that the field strength between both layers at any place becomes uniform.
JP11501879A 1979-09-07 1979-09-07 Semiconductor device Pending JPS5638852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11501879A JPS5638852A (en) 1979-09-07 1979-09-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11501879A JPS5638852A (en) 1979-09-07 1979-09-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5638852A true JPS5638852A (en) 1981-04-14

Family

ID=14652203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11501879A Pending JPS5638852A (en) 1979-09-07 1979-09-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5638852A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992557A (en) * 1982-11-18 1984-05-28 Nec Corp Semiconductor integrated circuit with input protection circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414172A (en) * 1977-07-04 1979-02-02 Seiko Epson Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414172A (en) * 1977-07-04 1979-02-02 Seiko Epson Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992557A (en) * 1982-11-18 1984-05-28 Nec Corp Semiconductor integrated circuit with input protection circuit
JPH0334659B2 (en) * 1982-11-18 1991-05-23 Nippon Electric Co

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