JPS5637645A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5637645A
JPS5637645A JP11244379A JP11244379A JPS5637645A JP S5637645 A JPS5637645 A JP S5637645A JP 11244379 A JP11244379 A JP 11244379A JP 11244379 A JP11244379 A JP 11244379A JP S5637645 A JPS5637645 A JP S5637645A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
layer
substrate
formed
accelerating voltage
injection layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11244379A
Inventor
Norio Endo
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE:To increase the degree of integration by providing wirings or resistances of buried type at the nonused portion within a semiconductor substrate. CONSTITUTION:A resist mask 4-1 is applied on an Si substrate and an O ion injection layer 2-1 formed with the proper accelerating voltage and dose amount. Another layer 2-2 is formed by injecting the ions again with the different accelerating voltage. Then, with a resist mask 4-2 having openings at different positions, an ion injection layer 2-3 is formed by controlling the accelerating voltage. Thereafter when the Si substrate is treated at high temperature, each ion injection layer is converted into SiO2, so that a buried layer surrounded by insulators is achieved. Next, a layer with a desired resistance value is obtained by ion-injecting an appropriate amount of impurities with the same or opposite type to that of the substrate into that surrounded region and the heat treating. This arrangement makes it possible that the degree of integration for the device is increased by utilizing the nonused portion in the substrate.
JP11244379A 1979-09-04 1979-09-04 Semiconductor device Pending JPS5637645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11244379A JPS5637645A (en) 1979-09-04 1979-09-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11244379A JPS5637645A (en) 1979-09-04 1979-09-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5637645A true true JPS5637645A (en) 1981-04-11

Family

ID=14586750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11244379A Pending JPS5637645A (en) 1979-09-04 1979-09-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5637645A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226808U (en) * 1985-08-01 1987-02-18
US4968636A (en) * 1988-09-14 1990-11-06 Oki Electric Industry Co., Ltd. Embedded isolation region and process for forming the same on silicon substrate
US6274422B1 (en) 1998-04-13 2001-08-14 Nec Corporation Method for manufacturing a semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6226808U (en) * 1985-08-01 1987-02-18
JPS6348025Y2 (en) * 1985-08-01 1988-12-12
US4968636A (en) * 1988-09-14 1990-11-06 Oki Electric Industry Co., Ltd. Embedded isolation region and process for forming the same on silicon substrate
US6274422B1 (en) 1998-04-13 2001-08-14 Nec Corporation Method for manufacturing a semiconductor device

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