JPS5635280A - Information reading device - Google Patents

Information reading device

Info

Publication number
JPS5635280A
JPS5635280A JP10974079A JP10974079A JPS5635280A JP S5635280 A JPS5635280 A JP S5635280A JP 10974079 A JP10974079 A JP 10974079A JP 10974079 A JP10974079 A JP 10974079A JP S5635280 A JPS5635280 A JP S5635280A
Authority
JP
Japan
Prior art keywords
output
circuit
converter
value
analog value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10974079A
Other languages
Japanese (ja)
Inventor
Kenzo Takeuchi
Shigeru Aiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10974079A priority Critical patent/JPS5635280A/en
Publication of JPS5635280A publication Critical patent/JPS5635280A/en
Pending legal-status Critical Current

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  • Character Input (AREA)

Abstract

PURPOSE: To realize a reading of the information with a reduced amount of errors and with a comparatively simple device, by holding the output of the line sensor at the peak value holding circuit and then dividing the sensor output to use for the reference voltage of the D/A converter.
CONSTITUTION: The output of the line sensor LNS is held at the peak value holding circuit PH, and the output of this circuit is divided by the resistance elements R1, and R2 to be applied to the operational amplifier OP. And the working point of the amplifier OP plus the values of the element R1 and R2 are selected so that the output of the OP may be turned into the voltage value of about 80% the output of the circuit PH. At the same time, the voltage value of 20% the output of the circuit PH is applied to the D/A converter in the form of the reference voltage. On the other hand, the brightest white signal among the memory MEM is applied to the D/A converter, and thus the analog value is obtained when the outout of the circuit PH changes and by the reference voltage according to the change of the output. This analog value is then amplified AMP, and then the output of the amplifier OP is piled on the analog value. Thus the analog value to which a sufficient correction of the white level has been given can be obtained. Accordingly, the working of the A/D converter 1 becomes accurate.
COPYRIGHT: (C)1981,JPO&Japio
JP10974079A 1979-08-30 1979-08-30 Information reading device Pending JPS5635280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10974079A JPS5635280A (en) 1979-08-30 1979-08-30 Information reading device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10974079A JPS5635280A (en) 1979-08-30 1979-08-30 Information reading device

Publications (1)

Publication Number Publication Date
JPS5635280A true JPS5635280A (en) 1981-04-07

Family

ID=14518040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10974079A Pending JPS5635280A (en) 1979-08-30 1979-08-30 Information reading device

Country Status (1)

Country Link
JP (1) JPS5635280A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174891A (en) * 1986-01-28 1987-07-31 Usac Electronics Ind Co Ltd High speed white level follower circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174891A (en) * 1986-01-28 1987-07-31 Usac Electronics Ind Co Ltd High speed white level follower circuit

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