JPS5626964U - - Google Patents
Info
- Publication number
- JPS5626964U JPS5626964U JP10907479U JP10907479U JPS5626964U JP S5626964 U JPS5626964 U JP S5626964U JP 10907479 U JP10907479 U JP 10907479U JP 10907479 U JP10907479 U JP 10907479U JP S5626964 U JPS5626964 U JP S5626964U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10907479U JPS6018849Y2 (en) | 1979-08-08 | 1979-08-08 | lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10907479U JPS6018849Y2 (en) | 1979-08-08 | 1979-08-08 | lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5626964U true JPS5626964U (en) | 1981-03-12 |
| JPS6018849Y2 JPS6018849Y2 (en) | 1985-06-07 |
Family
ID=29341673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10907479U Expired JPS6018849Y2 (en) | 1979-08-08 | 1979-08-08 | lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6018849Y2 (en) |
-
1979
- 1979-08-08 JP JP10907479U patent/JPS6018849Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6018849Y2 (en) | 1985-06-07 |