JPS56152333A - Phase synchronizing loop - Google Patents

Phase synchronizing loop

Info

Publication number
JPS56152333A
JPS56152333A JP5665380A JP5665380A JPS56152333A JP S56152333 A JPS56152333 A JP S56152333A JP 5665380 A JP5665380 A JP 5665380A JP 5665380 A JP5665380 A JP 5665380A JP S56152333 A JPS56152333 A JP S56152333A
Authority
JP
Japan
Prior art keywords
loop
phase
gain
detector
cnr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5665380A
Other languages
Japanese (ja)
Inventor
Yoichi Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5665380A priority Critical patent/JPS56152333A/en
Publication of JPS56152333A publication Critical patent/JPS56152333A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain an optimum phase synchronized performance, by detecting the ratio of noise power to signal power (CNR) of the input and by utilizing this detection quantity to adjust the gain of the sensitivity change loop of the phase detector. CONSTITUTION:A phase synchronizing loop is formed by input terminal 1, phase detector 2, loop filter 3, voltage variable gain loop amplifier 7, and voltage control oscillator 5. The phase error signal is generated in detector 2. Capacitor 8 takes out the error voltage only due to noise components, and noise components corresponding to CNR are rectified by full wave rectifying circuit 9. LPF10 smooths the rectification output to determine the control speed of the gain for amplifier 7. Though the sensitivity of detector 2 is changed by the change of CNR, the characteristic of the loop is always kept constant by giving the inverse gain change to amplifier 7.
JP5665380A 1980-04-25 1980-04-25 Phase synchronizing loop Pending JPS56152333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5665380A JPS56152333A (en) 1980-04-25 1980-04-25 Phase synchronizing loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5665380A JPS56152333A (en) 1980-04-25 1980-04-25 Phase synchronizing loop

Publications (1)

Publication Number Publication Date
JPS56152333A true JPS56152333A (en) 1981-11-25

Family

ID=13033322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5665380A Pending JPS56152333A (en) 1980-04-25 1980-04-25 Phase synchronizing loop

Country Status (1)

Country Link
JP (1) JPS56152333A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123232A (en) * 1982-01-08 1983-07-22 リトン・システムズ・インコ−ポレ−テツド Phase locked loop
US4568888A (en) * 1983-11-08 1986-02-04 Trw Inc. PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction
US4573026A (en) * 1984-02-29 1986-02-25 Hewlett-Packard Company FM Modulator phase-locked loop with FM calibration
US4602217A (en) * 1983-11-18 1986-07-22 Hitachi, Ltd. FM demodulator capable of shifting demodulation-band center frequency

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123232A (en) * 1982-01-08 1983-07-22 リトン・システムズ・インコ−ポレ−テツド Phase locked loop
US4568888A (en) * 1983-11-08 1986-02-04 Trw Inc. PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction
US4602217A (en) * 1983-11-18 1986-07-22 Hitachi, Ltd. FM demodulator capable of shifting demodulation-band center frequency
US4573026A (en) * 1984-02-29 1986-02-25 Hewlett-Packard Company FM Modulator phase-locked loop with FM calibration

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