JPS56130966A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56130966A
JPS56130966A JP3333680A JP3333680A JPS56130966A JP S56130966 A JPS56130966 A JP S56130966A JP 3333680 A JP3333680 A JP 3333680A JP 3333680 A JP3333680 A JP 3333680A JP S56130966 A JPS56130966 A JP S56130966A
Authority
JP
Japan
Prior art keywords
layer
wafer
type
electrodes
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3333680A
Other languages
Japanese (ja)
Inventor
Kazuo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3333680A priority Critical patent/JPS56130966A/en
Publication of JPS56130966A publication Critical patent/JPS56130966A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds

Abstract

PURPOSE:To enhance the reliability of a semiconductor device by forming a multilayer electrodes having a zirconium boride thin film as a basic layer directly or via intermetallic compound layer on the surface of a semiconductor element region. CONSTITUTION:Ti is covered on a P<+> type region 5' formed on N type silicon epitaxial wafers 3', 4', heated in argon gas, and a titanium silicide layer 12' is formed. 3-layer electrodes 14 formed of ZrB2 layer 13, Pt layer 7 and Au layer 8 are formed thereafter by vacuum evaporation. Therafter, the shape of the wafer is formed in a desired mesa type with TiSi2 shaping layer 12. Diode group thus formed is individually cut from the wafer, and mesa type semiconductor diodes 1 can be obtained.
JP3333680A 1980-03-18 1980-03-18 Semiconductor device Pending JPS56130966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3333680A JPS56130966A (en) 1980-03-18 1980-03-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3333680A JPS56130966A (en) 1980-03-18 1980-03-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56130966A true JPS56130966A (en) 1981-10-14

Family

ID=12383713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3333680A Pending JPS56130966A (en) 1980-03-18 1980-03-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56130966A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045408A (en) * 1986-09-19 1991-09-03 University Of California Thermodynamically stabilized conductor/compound semiconductor interfaces

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045408A (en) * 1986-09-19 1991-09-03 University Of California Thermodynamically stabilized conductor/compound semiconductor interfaces

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