JPS5545156A - Odd-even field decision circuit - Google Patents
Odd-even field decision circuitInfo
- Publication number
- JPS5545156A JPS5545156A JP11794278A JP11794278A JPS5545156A JP S5545156 A JPS5545156 A JP S5545156A JP 11794278 A JP11794278 A JP 11794278A JP 11794278 A JP11794278 A JP 11794278A JP S5545156 A JPS5545156 A JP S5545156A
- Authority
- JP
- Japan
- Prior art keywords
- synchronizing signal
- odd
- gate
- composite synchronizing
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To make decision on odd and even fields by a simple constitution when a video signal is recorded by VTR, by processing a composite synchronizing signal of the video signal by a counter, gate, etc.
CONSTITUTION: Once triggered by a composite synchronizing signal formed of equivalent pulses and a vertical synchronizing signal, monostable multivibrator 1 with a fixed time constant generates fixed gate pulses to open AND gate 2. As a result, counter 3 counts equivalent pulses extracted from the composite synchronizing signal passing through gate 2. When the count value reaches a fixed number, counter 3 triggers monostable multivibrator 4 to close AND gates 7 and 8 by the output of multivibrator 4 passing through differentiating circuit 5 and inverter 6. Therefore, field discrimination equivalent pulses are extracted by gates 7 and 8 as high-level signals in accordance with odd and even fields right after a fixed number of equivalent pulses in the composite synchronizing signal and inverted composite synchronizing signal applied to gates 7 and 8, so that decisions on odd and even fields can be made by simple constitution.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11794278A JPS5545156A (en) | 1978-09-27 | 1978-09-27 | Odd-even field decision circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11794278A JPS5545156A (en) | 1978-09-27 | 1978-09-27 | Odd-even field decision circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5545156A true JPS5545156A (en) | 1980-03-29 |
JPS6128186B2 JPS6128186B2 (en) | 1986-06-28 |
Family
ID=14724028
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11794278A Granted JPS5545156A (en) | 1978-09-27 | 1978-09-27 | Odd-even field decision circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5545156A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5146459A (en) * | 1986-11-28 | 1992-09-08 | Canon Kabushiki Kaisha | Electronic equipment with check-sum function |
-
1978
- 1978-09-27 JP JP11794278A patent/JPS5545156A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5146459A (en) * | 1986-11-28 | 1992-09-08 | Canon Kabushiki Kaisha | Electronic equipment with check-sum function |
Also Published As
Publication number | Publication date |
---|---|
JPS6128186B2 (en) | 1986-06-28 |
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