JPS55161441A - Pulse noise eliminating circuit - Google Patents

Pulse noise eliminating circuit

Info

Publication number
JPS55161441A
JPS55161441A JP6910679A JP6910679A JPS55161441A JP S55161441 A JPS55161441 A JP S55161441A JP 6910679 A JP6910679 A JP 6910679A JP 6910679 A JP6910679 A JP 6910679A JP S55161441 A JPS55161441 A JP S55161441A
Authority
JP
Japan
Prior art keywords
signal
circuit
pilot signal
input
cancel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6910679A
Other languages
Japanese (ja)
Inventor
Hiroyasu Kishi
Sadao Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP6910679A priority Critical patent/JPS55161441A/en
Priority to US06/133,932 priority patent/US4314377A/en
Priority to CA000348551A priority patent/CA1144081A/en
Priority to DE8080102251T priority patent/DE3067514D1/en
Priority to EP80102251A priority patent/EP0018608B1/en
Publication of JPS55161441A publication Critical patent/JPS55161441A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/72—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/1646—Circuits adapted for the reception of stereophonic signals
    • H04B1/1653—Detection of the presence of stereo signals and pilot signal regeneration

Abstract

PURPOSE:To prevent the influence of a stereo pilot signal, by synthesizing the stereo pilot signal and a cancel signal, which has a prescribed phase relation for this signal, to prevent the pilot signal from being included in the input signal of a demodulating circuit. CONSTITUTION:In case of no noise in input, the normal stereo pilot signal and the low frequency signal from signal synthesizing circuit 16 and gate circuit 4 and a cancel signal obtained by shaping the waveform of the pilot signal into a prescribed phase through extracting circuit 8, frequency divider 14 and waveform shaping circuit 18 are synthesized to eliminate the pilot signal. When noise generates, gates 4 and 21 are cut off. Therefore, the signal having the level just before cutoff of circuit 4 held in holding means 5 and the signal having the level just before cutoff of circuit 21 are input to circuit 16 from holding means 22. This, the pilot signal is eliminated by the cancel signal to have no bad influence upon demodulating circuit 17.
JP6910679A 1979-04-27 1979-06-01 Pulse noise eliminating circuit Pending JPS55161441A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP6910679A JPS55161441A (en) 1979-06-01 1979-06-01 Pulse noise eliminating circuit
US06/133,932 US4314377A (en) 1979-04-27 1980-03-25 Noise removing apparatus
CA000348551A CA1144081A (en) 1979-04-27 1980-03-25 Noise removing apparatus
DE8080102251T DE3067514D1 (en) 1979-04-27 1980-04-25 A noise removing apparatus
EP80102251A EP0018608B1 (en) 1979-04-27 1980-04-25 A noise removing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6910679A JPS55161441A (en) 1979-06-01 1979-06-01 Pulse noise eliminating circuit

Publications (1)

Publication Number Publication Date
JPS55161441A true JPS55161441A (en) 1980-12-16

Family

ID=13393036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6910679A Pending JPS55161441A (en) 1979-04-27 1979-06-01 Pulse noise eliminating circuit

Country Status (1)

Country Link
JP (1) JPS55161441A (en)

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