JPS5513486A - Figure display method - Google Patents

Figure display method

Info

Publication number
JPS5513486A
JPS5513486A JP8654278A JP8654278A JPS5513486A JP S5513486 A JPS5513486 A JP S5513486A JP 8654278 A JP8654278 A JP 8654278A JP 8654278 A JP8654278 A JP 8654278A JP S5513486 A JPS5513486 A JP S5513486A
Authority
JP
Japan
Prior art keywords
decimal point
data
circuit
sent
point data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8654278A
Other languages
Japanese (ja)
Inventor
Takayoshi Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8654278A priority Critical patent/JPS5513486A/en
Publication of JPS5513486A publication Critical patent/JPS5513486A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a simultaneous display for both the next figure data and the decimal point data through a simple constitution by memorizing the read-out decimal point data into FF and at the same time sending the decimal point data to the counter to give an advance by one count.
CONSTITUTION: The data read out of memory M is sent to display circuit S and decimal point decision circuit D. When the decimal point data is detected at circuit D, the detection pulse signal is sent to FF circuit F to be memorized as well as sent to counter R via clock signal generation circuit C for advance of the pulse count by one. On the other hand, the output signal of circuit F is sent to circuit S in the form of the decimal point display signal, and thus the following figure data of memory M is read out. Thus both the figure data and the decimal point data are displayed at one time. In such way, both the next figure data and the decimal point data can be displayed simultaneously through a simple constitution and without using any complicated decimal point process circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP8654278A 1978-07-15 1978-07-15 Figure display method Pending JPS5513486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8654278A JPS5513486A (en) 1978-07-15 1978-07-15 Figure display method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8654278A JPS5513486A (en) 1978-07-15 1978-07-15 Figure display method

Publications (1)

Publication Number Publication Date
JPS5513486A true JPS5513486A (en) 1980-01-30

Family

ID=13889882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8654278A Pending JPS5513486A (en) 1978-07-15 1978-07-15 Figure display method

Country Status (1)

Country Link
JP (1) JPS5513486A (en)

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