JPS55110437A - Saving circuit for radio communication unit - Google Patents

Saving circuit for radio communication unit

Info

Publication number
JPS55110437A
JPS55110437A JP1708979A JP1708979A JPS55110437A JP S55110437 A JPS55110437 A JP S55110437A JP 1708979 A JP1708979 A JP 1708979A JP 1708979 A JP1708979 A JP 1708979A JP S55110437 A JPS55110437 A JP S55110437A
Authority
JP
Japan
Prior art keywords
high level
output
circuit
signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1708979A
Other languages
Japanese (ja)
Other versions
JPS6056339B2 (en
Inventor
Hiroshi Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Gen Co Ltd
Original Assignee
Fujitsu General Ltd
Gen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gen Co Ltd filed Critical Fujitsu General Ltd
Priority to JP54017089A priority Critical patent/JPS6056339B2/en
Publication of JPS55110437A publication Critical patent/JPS55110437A/en
Publication of JPS6056339B2 publication Critical patent/JPS6056339B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • H04W52/0241—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal where no transmission is received, e.g. out of range of the transmitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transceivers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

PURPOSE:To efficiently perform saving, by taking low level for the output of the squelch circuit if no signal input is present at the reception section and holding the output of delay latch circuit at high level until the next intermittent signal is high level if the reception input is present. CONSTITUTION:In the saving circuit in which the wear of battery of a portable radio set is minimized, the intermittent signal generator 11 consisting of self-running multivibrator is coupled with the reception section 13 via the OR gate 12 to control ON and OFF of the power supply. Further, if no signal enters the reception section 13, the output of the squelch circuit 15 is low level, the output of the delay latch circuit 17 is also at low level, and the output of the OR gate 12 turns on and off the power supply for saving operation. Next, when the objective signal enters the antenna 14 and the next intermittent signal is at high level, high level signal appears at the circuit 15 to make high level the output of the AND gate 16 and to latch the circuit 17 at high level, and the power supply of the reception section 13 is turned on via the gate 12 until the next intermittent signal is at high level. Thus, efficient saving can be achieved.
JP54017089A 1979-02-16 1979-02-16 Wireless communication device saving circuit Expired JPS6056339B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54017089A JPS6056339B2 (en) 1979-02-16 1979-02-16 Wireless communication device saving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54017089A JPS6056339B2 (en) 1979-02-16 1979-02-16 Wireless communication device saving circuit

Publications (2)

Publication Number Publication Date
JPS55110437A true JPS55110437A (en) 1980-08-25
JPS6056339B2 JPS6056339B2 (en) 1985-12-10

Family

ID=11934251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54017089A Expired JPS6056339B2 (en) 1979-02-16 1979-02-16 Wireless communication device saving circuit

Country Status (1)

Country Link
JP (1) JPS6056339B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119246U (en) * 1982-02-04 1983-08-13 日本電気株式会社 Receiver power control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119246U (en) * 1982-02-04 1983-08-13 日本電気株式会社 Receiver power control circuit

Also Published As

Publication number Publication date
JPS6056339B2 (en) 1985-12-10

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