JPS55100770A - Clock regenerating device - Google Patents

Clock regenerating device

Info

Publication number
JPS55100770A
JPS55100770A JP957279A JP957279A JPS55100770A JP S55100770 A JPS55100770 A JP S55100770A JP 957279 A JP957279 A JP 957279A JP 957279 A JP957279 A JP 957279A JP S55100770 A JPS55100770 A JP S55100770A
Authority
JP
Japan
Prior art keywords
clock
circuit
signal
digital signal
quad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP957279A
Other languages
Japanese (ja)
Other versions
JPS596541B2 (en
Inventor
Masaharu Araki
Izumi Horikawa
Yoichi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54009572A priority Critical patent/JPS596541B2/en
Publication of JPS55100770A publication Critical patent/JPS55100770A/en
Publication of JPS596541B2 publication Critical patent/JPS596541B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To regenerate a clock signal without any phase error by suppressing the phase jitter component of a clock signal due to the pattern of a digital signal when extracting a clock component from the digital signal itself to be transmitted. CONSTITUTION:A base-band quad digital signal is applied from delay circuit 17 to 1st clock extraction circuit 16, composed of clock extraction circuit 2, turning amplifier circuit 5 and limiter 6, and also to discrimination circuit 10 and two sequences of binary signals are regenerated by the regenerating clock signal of voltage control oscillator 9 and outputted to output terminals 18 and 19. Those outputs are converted by binary/quad converter 14 into a quad signal, which is also converted into a local digital signal by transmission-system filter 15. This signal is supplied to 2nd clock extraction circuit 22 as well as circuit 16; and outputs of 1st and 2nd clock extraction circuits are compared by a phase comparator and after the phase jitter component is removed, the output of the comparator is supplied to loop filter 8, where the phase error is removed and applied to circuit 9 as a normal clock.
JP54009572A 1979-01-29 1979-01-29 clock regenerator Expired JPS596541B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54009572A JPS596541B2 (en) 1979-01-29 1979-01-29 clock regenerator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54009572A JPS596541B2 (en) 1979-01-29 1979-01-29 clock regenerator

Publications (2)

Publication Number Publication Date
JPS55100770A true JPS55100770A (en) 1980-07-31
JPS596541B2 JPS596541B2 (en) 1984-02-13

Family

ID=11724009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54009572A Expired JPS596541B2 (en) 1979-01-29 1979-01-29 clock regenerator

Country Status (1)

Country Link
JP (1) JPS596541B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58170145A (en) * 1982-03-15 1983-10-06 トムソン−セ−エスエフ Clock frequency reproduction repeating device in digital transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58170145A (en) * 1982-03-15 1983-10-06 トムソン−セ−エスエフ Clock frequency reproduction repeating device in digital transmission

Also Published As

Publication number Publication date
JPS596541B2 (en) 1984-02-13

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