JPS5485650A - Branch instruction control system - Google Patents

Branch instruction control system

Info

Publication number
JPS5485650A
JPS5485650A JP15291177A JP15291177A JPS5485650A JP S5485650 A JPS5485650 A JP S5485650A JP 15291177 A JP15291177 A JP 15291177A JP 15291177 A JP15291177 A JP 15291177A JP S5485650 A JPS5485650 A JP S5485650A
Authority
JP
Japan
Prior art keywords
instruction
unit
bus
fed
branch instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15291177A
Other languages
Japanese (ja)
Inventor
Kanji Kubo
Chikahiko Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15291177A priority Critical patent/JPS5485650A/en
Publication of JPS5485650A publication Critical patent/JPS5485650A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the branch instruction processing without causing the competition with the main stream instruction for the processing due to advanced instruction for branch, by interpreting the branch instruction advanced independently of normal instruction processing and performing address calculation.
CONSTITUTION: The memory unit control S 1 controls the access to the memory unit by the instruction control I unit(consisting of B,O subunits) or the operation E unit 3. Althought the branch instruction can be picked up from the instruction in the buffer in the B subunit, this branch instruction is entirely independently picked up from the normal sequence of instruction processing fed to the unit 13 with the bus 14 and is fed to the unit 13 with the bus 15. Next, the unit 13 interpretes the branch instruction fed from the bus 15 entirely independently of the interpretation and address calculation of instruction fed with the bus 14, calculates the branched address, and the branched address obtained is fed to the unit 12 with the bus 16.
COPYRIGHT: (C)1979,JPO&Japio
JP15291177A 1977-12-21 1977-12-21 Branch instruction control system Pending JPS5485650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15291177A JPS5485650A (en) 1977-12-21 1977-12-21 Branch instruction control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15291177A JPS5485650A (en) 1977-12-21 1977-12-21 Branch instruction control system

Publications (1)

Publication Number Publication Date
JPS5485650A true JPS5485650A (en) 1979-07-07

Family

ID=15550826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15291177A Pending JPS5485650A (en) 1977-12-21 1977-12-21 Branch instruction control system

Country Status (1)

Country Link
JP (1) JPS5485650A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226232A (en) * 1986-03-28 1987-10-05 Toshiba Corp Control system for branch instruction
JPH02227731A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Data processing system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121449A (en) * 1973-03-19 1974-11-20
JPS5039437A (en) * 1973-08-10 1975-04-11

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121449A (en) * 1973-03-19 1974-11-20
JPS5039437A (en) * 1973-08-10 1975-04-11

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226232A (en) * 1986-03-28 1987-10-05 Toshiba Corp Control system for branch instruction
JPH056894B2 (en) * 1986-03-28 1993-01-27 Tokyo Shibaura Electric Co
JPH02227731A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Data processing system

Similar Documents

Publication Publication Date Title
JPS5387640A (en) Data processing unit
JPS53102643A (en) Interrupt processing system for computer
JPS5485650A (en) Branch instruction control system
JPS51138355A (en) Processing apparatus with a high speed branching feature
JPS5282149A (en) Instruction address control system
JPS5235946A (en) Memory control unit
JPS5419627A (en) Collation system for data processing unit
JPS51130138A (en) Data processing system for extended instructions
JPS5534316A (en) Store buffer control system
JPS5346245A (en) Microprogram controller
JPS53140948A (en) Interrupt processing system
JPS5427750A (en) Input-output processing method of virtual space segment
JPS5235947A (en) Information processing unit for imaginary memory system
JPS5390832A (en) Microorder bus time-division controller
JPS52100947A (en) Advanced control system
JPS522142A (en) Interruption preference deciding system
JPS5436148A (en) Interruption control method for electronic computer
JPS5332639A (en) Arithmetic operation unit
JPS5335447A (en) Multi processor system
JPS5474650A (en) Stack control system
JPS53148343A (en) Post store control system
JPS53129940A (en) Branch process system for processor
JPS5427737A (en) Bus control system
JPS5429535A (en) Data processing system
JPS5419622A (en) Control system for response confirmation