JPS5423566U - - Google Patents
Info
- Publication number
- JPS5423566U JPS5423566U JP9656477U JP9656477U JPS5423566U JP S5423566 U JPS5423566 U JP S5423566U JP 9656477 U JP9656477 U JP 9656477U JP 9656477 U JP9656477 U JP 9656477U JP S5423566 U JPS5423566 U JP S5423566U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9656477U JPS5423566U (en) | 1977-07-19 | 1977-07-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9656477U JPS5423566U (en) | 1977-07-19 | 1977-07-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5423566U true JPS5423566U (en) | 1979-02-16 |
Family
ID=29030561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9656477U Pending JPS5423566U (en) | 1977-07-19 | 1977-07-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5423566U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5129872A (en) * | 1974-09-06 | 1976-03-13 | Hitachi Ltd | KINZOKUKI BANNOSET SUZOKUHOHO |
-
1977
- 1977-07-19 JP JP9656477U patent/JPS5423566U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5129872A (en) * | 1974-09-06 | 1976-03-13 | Hitachi Ltd | KINZOKUKI BANNOSET SUZOKUHOHO |