JPS5389639A - Parityycontained current mode 55bit arithmetic logic device - Google Patents

Parityycontained current mode 55bit arithmetic logic device

Info

Publication number
JPS5389639A
JPS5389639A JP15855577A JP15855577A JPS5389639A JP S5389639 A JPS5389639 A JP S5389639A JP 15855577 A JP15855577 A JP 15855577A JP 15855577 A JP15855577 A JP 15855577A JP S5389639 A JPS5389639 A JP S5389639A
Authority
JP
Japan
Prior art keywords
parityycontained
55bit
logic device
current mode
arithmetic logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15855577A
Other languages
English (en)
Japanese (ja)
Other versions
JPS618971B2 (https=
Inventor
Waanaa Miraa Hoomaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5389639A publication Critical patent/JPS5389639A/ja
Publication of JPS618971B2 publication Critical patent/JPS618971B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4806—Cascode or current mode logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
  • Logic Circuits (AREA)
JP15855577A 1977-01-03 1977-12-27 Parityycontained current mode 55bit arithmetic logic device Granted JPS5389639A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/756,456 US4084252A (en) 1977-01-03 1977-01-03 Current mode 5-bit arithmetic logic unit with parity

Publications (2)

Publication Number Publication Date
JPS5389639A true JPS5389639A (en) 1978-08-07
JPS618971B2 JPS618971B2 (https=) 1986-03-19

Family

ID=25043570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15855577A Granted JPS5389639A (en) 1977-01-03 1977-12-27 Parityycontained current mode 55bit arithmetic logic device

Country Status (2)

Country Link
US (1) US4084252A (https=)
JP (1) JPS5389639A (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4298952A (en) * 1979-12-10 1981-11-03 Honeywell Information Systems Inc. One's complement adder
US4608693A (en) * 1984-05-07 1986-08-26 At&T Bell Laboratories Fault detection arrangement for a digital conferencing system
US5175862A (en) * 1989-12-29 1992-12-29 Supercomputer Systems Limited Partnership Method and apparatus for a special purpose arithmetic boolean unit
US6343306B1 (en) 1999-05-18 2002-01-29 Sun Microsystems, Inc. High speed one's complement adder

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2056229A5 (https=) * 1969-07-31 1971-05-14 Ibm
US3758760A (en) * 1972-04-07 1973-09-11 Honeywell Inf Systems Error detection for arithmetic and logical unit modules
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder
US3986015A (en) * 1975-06-23 1976-10-12 International Business Machines Corporation Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection

Also Published As

Publication number Publication date
US4084252A (en) 1978-04-11
JPS618971B2 (https=) 1986-03-19

Similar Documents

Publication Publication Date Title
JPS57197649A (en) Arithmetic logic device
NZ185499A (en) Protectine glove
CS188180A2 (en) Zpusob vyroby adsorpcniho cinidla pro afinitne specificke deleni nukleovych kyselin
JPS52143A (en) Arithmetic unit
GB1546527A (en) Conduct means
JPS523352A (en) Arithmetic operating unit
CS755278A1 (en) Zarizeni pro elektrojiskrove nanaseni
CS175678A1 (en) Dvojkoli pro ruzne rozchody
GB1551896A (en) Multiply-divide unit
CS590878A2 (en) Zarizeni pro bezvretenove predeni
JPS52116032A (en) Parallel arithmetic unit
JPS5317872A (en) Vehicleedecelerating device using eddy current
JPS5440554A (en) Logic function device
JPS5398053A (en) Electric part
JPS5379280A (en) Nonnarcing switch
JPS5389639A (en) Parityycontained current mode 55bit arithmetic logic device
JPS53108253A (en) Current mode 44bit arithmetic logic unit having parity
JPS5331693A (en) Antiibacterial agents
ZA776821B (en) Antirhinovirus agents
CS610278A1 (en) Zarizeni pro dopravu kapalin v nadobach
ZA776789B (en) Antirhinovirus agents
CS292881A2 (en) Ovladatelna spojka pro spojeni hridelu dvou jednotek spalo vaciho motoru
JPS5340876A (en) Switch
JPS52152698A (en) Escaping unit
JPS5292666A (en) Wash unit