JPS5343082Y2 - - Google Patents

Info

Publication number
JPS5343082Y2
JPS5343082Y2 JP6772872U JP6772872U JPS5343082Y2 JP S5343082 Y2 JPS5343082 Y2 JP S5343082Y2 JP 6772872 U JP6772872 U JP 6772872U JP 6772872 U JP6772872 U JP 6772872U JP S5343082 Y2 JPS5343082 Y2 JP S5343082Y2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6772872U
Other languages
Japanese (ja)
Other versions
JPS4926469U (cs
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6772872U priority Critical patent/JPS5343082Y2/ja
Publication of JPS4926469U publication Critical patent/JPS4926469U/ja
Application granted granted Critical
Publication of JPS5343082Y2 publication Critical patent/JPS5343082Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP6772872U 1972-06-08 1972-06-08 Expired JPS5343082Y2 (cs)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6772872U JPS5343082Y2 (cs) 1972-06-08 1972-06-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6772872U JPS5343082Y2 (cs) 1972-06-08 1972-06-08

Publications (2)

Publication Number Publication Date
JPS4926469U JPS4926469U (cs) 1974-03-06
JPS5343082Y2 true JPS5343082Y2 (cs) 1978-10-17

Family

ID=27962602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6772872U Expired JPS5343082Y2 (cs) 1972-06-08 1972-06-08

Country Status (1)

Country Link
JP (1) JPS5343082Y2 (cs)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54137794U (cs) * 1978-03-11 1979-09-25
JPS54137795U (cs) * 1978-03-11 1979-09-25
JPS58176528U (ja) * 1982-05-21 1983-11-25 岩「淵」金属工業株式会社 メツセンジヤ−ワイヤ−用電柱支持金具

Also Published As

Publication number Publication date
JPS4926469U (cs) 1974-03-06

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