JPS5232557B2 - - Google Patents
Info
- Publication number
- JPS5232557B2 JPS5232557B2 JP47026256A JP2625672A JPS5232557B2 JP S5232557 B2 JPS5232557 B2 JP S5232557B2 JP 47026256 A JP47026256 A JP 47026256A JP 2625672 A JP2625672 A JP 2625672A JP S5232557 B2 JPS5232557 B2 JP S5232557B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Semiconductor Memories (AREA)
- Electronic Switches (AREA)
Priority Applications (20)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47026256A JPS5232557B2 (US06811534-20041102-M00003.png) | 1972-03-14 | 1972-03-14 | |
| GB1074073A GB1357515A (en) | 1972-03-10 | 1973-03-06 | Method for manufacturing an mos integrated circuit |
| FR7308327A FR2175819B1 (US06811534-20041102-M00003.png) | 1972-03-10 | 1973-03-08 | |
| DE2311913A DE2311913A1 (de) | 1972-03-10 | 1973-03-09 | Verfahren zur herstellung von matrixkreisen mit parallelgattern |
| DE19732311915 DE2311915B2 (de) | 1972-03-10 | 1973-03-09 | Verfahren zur herstellung von elektrisch leitenden verbindungen zwischen source- und drain-bereichen in integrierten mos-schaltkreisen |
| US340254A US3865650A (en) | 1972-03-10 | 1973-03-12 | Method for manufacturing a MOS integrated circuit |
| US340255A US3865651A (en) | 1972-03-10 | 1973-03-12 | Method of manufacturing series gate type matrix circuits |
| DE2312414A DE2312414C2 (de) | 1972-03-10 | 1973-03-13 | Verfahren zur Herstellung von integrierten MOSFET-Schaltkreisen |
| GB1190273A GB1430301A (en) | 1972-03-10 | 1973-03-13 | Method of manufacturing mos matrix circuits |
| IT4876573A IT979822B (it) | 1972-03-14 | 1973-03-13 | Procedimento per la produzione di circuiti di matrice del tipo a controllo in serie |
| GB1190173A GB1375355A (US06811534-20041102-M00003.png) | 1972-03-10 | 1973-03-13 | |
| CA165,982A CA1009379A (en) | 1972-03-10 | 1973-03-13 | Method of manufacturing parallel gate type matrix circuits |
| FR7308860A FR2175960B1 (US06811534-20041102-M00003.png) | 1972-03-10 | 1973-03-13 | |
| FR7308863A FR2175961B1 (US06811534-20041102-M00003.png) | 1972-03-10 | 1973-03-13 | |
| DE19732312413 DE2312413B2 (de) | 1972-03-10 | 1973-03-13 | Verfahren zur herstellung eines matrixschaltkreises |
| GB1234073A GB1357516A (en) | 1972-03-10 | 1973-03-14 | Method of manufacturing an mos integrated circuit |
| US341493A US3874955A (en) | 1972-03-10 | 1973-03-15 | Method of manufacturing an mos integrated circuit |
| CA166,294A CA978661A (en) | 1972-03-10 | 1973-03-16 | Method of manufacturing an mos integrated circuit |
| FR7309581A FR2176825B1 (US06811534-20041102-M00003.png) | 1972-03-10 | 1973-03-16 | |
| US05/560,735 US3985591A (en) | 1972-03-10 | 1975-03-21 | Method of manufacturing parallel gate matrix circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47026256A JPS5232557B2 (US06811534-20041102-M00003.png) | 1972-03-14 | 1972-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4894377A JPS4894377A (US06811534-20041102-M00003.png) | 1973-12-05 |
| JPS5232557B2 true JPS5232557B2 (US06811534-20041102-M00003.png) | 1977-08-22 |
Family
ID=12188165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP47026256A Expired JPS5232557B2 (US06811534-20041102-M00003.png) | 1972-03-10 | 1972-03-14 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5232557B2 (US06811534-20041102-M00003.png) |
| IT (1) | IT979822B (US06811534-20041102-M00003.png) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5525502B2 (US06811534-20041102-M00003.png) * | 1973-08-31 | 1980-07-07 | ||
| JPS5947464B2 (ja) * | 1974-09-11 | 1984-11-19 | 株式会社日立製作所 | 半導体装置 |
| JPS5851427B2 (ja) * | 1975-09-04 | 1983-11-16 | 株式会社日立製作所 | 絶縁ゲ−ト型リ−ド・オンリ−・メモリの製造方法 |
| US4059826A (en) * | 1975-12-29 | 1977-11-22 | Texas Instruments Incorporated | Semiconductor memory array with field effect transistors programmable by alteration of threshold voltage |
| JPS5373962A (en) * | 1976-12-14 | 1978-06-30 | Toshiba Corp | Logic circuit |
| JPS6028144B2 (ja) * | 1983-08-24 | 1985-07-03 | 株式会社日立製作所 | Ｍｉｓ形半導体装置の製法 |
-
1972
- 1972-03-14 JP JP47026256A patent/JPS5232557B2/ja not_active Expired
-
1973
- 1973-03-13 IT IT4876573A patent/IT979822B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| IT979822B (it) | 1974-09-30 |
| JPS4894377A (US06811534-20041102-M00003.png) | 1973-12-05 |
