JPS52104868A - Semiconductor - Google Patents

Semiconductor

Info

Publication number
JPS52104868A
JPS52104868A JP2108476A JP2108476A JPS52104868A JP S52104868 A JPS52104868 A JP S52104868A JP 2108476 A JP2108476 A JP 2108476A JP 2108476 A JP2108476 A JP 2108476A JP S52104868 A JPS52104868 A JP S52104868A
Authority
JP
Japan
Prior art keywords
glass
oxide film
insulating layer
semiconductor
sholder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2108476A
Other languages
Japanese (ja)
Other versions
JPS5633861B2 (en
Inventor
Kensuke Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2108476A priority Critical patent/JPS52104868A/en
Publication of JPS52104868A publication Critical patent/JPS52104868A/en
Publication of JPS5633861B2 publication Critical patent/JPS5633861B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To make it possible to apply glass flow method at lower temperature, by implanting impurity ions into partially or whole region of an insulating layer formed on an oxide film, forming the oxide film made of glass having lower m.p. than the insulating layer and smoothing sholder-shaped portions of the surface of the glass layer by heating.
COPYRIGHT: (C)1977,JPO&Japio
JP2108476A 1976-03-01 1976-03-01 Semiconductor Granted JPS52104868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2108476A JPS52104868A (en) 1976-03-01 1976-03-01 Semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2108476A JPS52104868A (en) 1976-03-01 1976-03-01 Semiconductor

Publications (2)

Publication Number Publication Date
JPS52104868A true JPS52104868A (en) 1977-09-02
JPS5633861B2 JPS5633861B2 (en) 1981-08-06

Family

ID=12045004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2108476A Granted JPS52104868A (en) 1976-03-01 1976-03-01 Semiconductor

Country Status (1)

Country Link
JP (1) JPS52104868A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4945626A (en) * 1972-09-01 1974-05-01
JPS5261479A (en) * 1975-11-17 1977-05-20 Mitsubishi Electric Corp Production of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4945626A (en) * 1972-09-01 1974-05-01
JPS5261479A (en) * 1975-11-17 1977-05-20 Mitsubishi Electric Corp Production of semiconductor device

Also Published As

Publication number Publication date
JPS5633861B2 (en) 1981-08-06

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