JPS5115344A - Heiretsushiki 2 shinkasanki - Google Patents

Heiretsushiki 2 shinkasanki

Info

Publication number
JPS5115344A
JPS5115344A JP50072768A JP7276875A JPS5115344A JP S5115344 A JPS5115344 A JP S5115344A JP 50072768 A JP50072768 A JP 50072768A JP 7276875 A JP7276875 A JP 7276875A JP S5115344 A JPS5115344 A JP S5115344A
Authority
JP
Japan
Prior art keywords
shinkasanki
heiretsushiki
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50072768A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5426462B2 (enExample
Inventor
Aaru Gengu Herumuuto
Hauju Johaan
Kunauto Gyuntaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19742432450 external-priority patent/DE2432450C2/de
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5115344A publication Critical patent/JPS5115344A/ja
Publication of JPS5426462B2 publication Critical patent/JPS5426462B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP50072768A 1974-07-06 1975-06-17 Heiretsushiki 2 shinkasanki Granted JPS5115344A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742432450 DE2432450C2 (de) 1974-07-06 Binäres Parallelrechenwerk für Additionen oder Subtraktionen

Publications (2)

Publication Number Publication Date
JPS5115344A true JPS5115344A (en) 1976-02-06
JPS5426462B2 JPS5426462B2 (enExample) 1979-09-04

Family

ID=5919845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50072768A Granted JPS5115344A (en) 1974-07-06 1975-06-17 Heiretsushiki 2 shinkasanki

Country Status (4)

Country Link
US (1) US3947671A (enExample)
JP (1) JPS5115344A (enExample)
FR (1) FR2277376A1 (enExample)
IT (1) IT1038941B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319335A (en) * 1979-10-16 1982-03-09 Burroughs Corporation Arithmetic logic unit controller
US4338676A (en) * 1980-07-14 1982-07-06 Bell Telephone Laboratories, Incorporated Asynchronous adder circuit
US4623981A (en) 1983-09-20 1986-11-18 Digital Equipment Corporation ALU with carry length detection
US4707783A (en) * 1984-10-19 1987-11-17 Amdahl Corporation Ancillary execution unit for a pipelined data processing system
US4885716A (en) * 1988-08-15 1989-12-05 Dallas Semiconductor Corporation High speed carry chain
JPH02259926A (ja) * 1989-03-31 1990-10-22 Hitachi Ltd 加算制御方式
US5327368A (en) * 1989-06-23 1994-07-05 Digital Equipment Corporation Chunky binary multiplier and method of operation
DE19639935C1 (de) * 1996-09-27 1998-04-23 Siemens Ag Schaltungsanordnung mit zwischen Registern angeordneten kombinatorischen Blöcken
AU2002317928A1 (en) * 2001-06-13 2003-05-19 Zencod S.A. Cryptographic processing accelerator board
RU2628180C1 (ru) * 2016-10-03 2017-08-15 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Арифметико-логическое устройство для сложения чисел по модулю
RU2628175C1 (ru) * 2016-10-12 2017-08-15 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Арифметико-логическое устройство для вычитания чисел по модулю

Also Published As

Publication number Publication date
US3947671A (en) 1976-03-30
IT1038941B (it) 1979-11-30
DE2432450B1 (de) 1975-12-04
FR2277376A1 (fr) 1976-01-30
DE2432450A1 (enExample) 1975-12-04
FR2277376B1 (enExample) 1977-07-08
JPS5426462B2 (enExample) 1979-09-04

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