JPS4915377B1 - - Google Patents
Info
- Publication number
- JPS4915377B1 JPS4915377B1 JP43071852A JP7185268A JPS4915377B1 JP S4915377 B1 JPS4915377 B1 JP S4915377B1 JP 43071852 A JP43071852 A JP 43071852A JP 7185268 A JP7185268 A JP 7185268A JP S4915377 B1 JPS4915377 B1 JP S4915377B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/92—Controlling diffusion profile by oxidation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43071852A JPS4915377B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1968-10-04 | 1968-10-04 | |
| US00862438A US3745070A (en) | 1968-10-04 | 1969-09-30 | Method of manufacturing semiconductor devices |
| GB1239684D GB1239684A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1968-10-04 | 1969-10-02 | |
| FR6933855A FR2023314A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1968-10-04 | 1969-10-03 | |
| DE1950069A DE1950069B2 (de) | 1968-10-04 | 1969-10-03 | Verfahren zum Herstellung einer Halbleiteranordnung |
| NL6914952A NL6914952A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1968-10-04 | 1969-10-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43071852A JPS4915377B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1968-10-04 | 1968-10-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS4915377B1 true JPS4915377B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1974-04-15 |
Family
ID=13472467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP43071852A Pending JPS4915377B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1968-10-04 | 1968-10-04 |
Country Status (6)
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3895965A (en) * | 1971-05-24 | 1975-07-22 | Bell Telephone Labor Inc | Method of forming buried layers by ion implantation |
| FR2209217B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1972-11-10 | 1977-12-16 | Lignes Telegraph Telephon | |
| US3852119A (en) * | 1972-11-14 | 1974-12-03 | Texas Instruments Inc | Metal-insulator-semiconductor structures having reduced junction capacitance and method of fabrication |
| US3966501A (en) * | 1973-03-23 | 1976-06-29 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
| US3959025A (en) * | 1974-05-01 | 1976-05-25 | Rca Corporation | Method of making an insulated gate field effect transistor |
| DE2507613C3 (de) * | 1975-02-21 | 1979-07-05 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung eines invers betriebenen Transistors |
| US4038106A (en) * | 1975-04-30 | 1977-07-26 | Rca Corporation | Four-layer trapatt diode and method for making same |
| US4055443A (en) * | 1975-06-19 | 1977-10-25 | Jury Stepanovich Akimov | Method for producing semiconductor matrix of light-emitting elements utilizing ion implantation and diffusion heating |
| US4055444A (en) * | 1976-01-12 | 1977-10-25 | Texas Instruments Incorporated | Method of making N-channel MOS integrated circuits |
| US4092209A (en) * | 1976-12-30 | 1978-05-30 | Rca Corp. | Silicon implanted and bombarded with phosphorus ions |
| US4168990A (en) * | 1977-04-04 | 1979-09-25 | International Rectifier Corporation | Hot implantation at 1100°-1300° C. for forming non-gaussian impurity profile |
| US4218267A (en) * | 1979-04-23 | 1980-08-19 | Rockwell International Corporation | Microelectronic fabrication method minimizing threshold voltage variation |
| DE3118785A1 (de) * | 1981-05-12 | 1982-12-02 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und vorrichtung zum dotieren von halbleitermaterial |
| JPS6065528A (ja) * | 1983-09-21 | 1985-04-15 | Hitachi Ltd | pn接合形成法 |
| US4818711A (en) * | 1987-08-28 | 1989-04-04 | Intel Corporation | High quality oxide on an ion implanted polysilicon surface |
| AU5779200A (en) | 1999-07-01 | 2001-01-22 | E-Ink Corporation | Electrophoretic medium provided with spacers |
| US7893435B2 (en) | 2000-04-18 | 2011-02-22 | E Ink Corporation | Flexible electronic circuits and displays including a backplane comprising a patterned metal foil having a plurality of apertures extending therethrough |
| CN1237623C (zh) | 2000-04-18 | 2006-01-18 | 伊英克公司 | 在衬底上成形晶体管的方法和含聚亚苯基聚酰亚胺的衬底 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1150454B (de) * | 1960-11-14 | 1963-06-20 | Licentia Gmbh | Verfahren zum Herstellen von pn-UEbergaengen in Siliziumscheiben |
| US3158505A (en) * | 1962-07-23 | 1964-11-24 | Fairchild Camera Instr Co | Method of placing thick oxide coatings on silicon and article |
| NL302630A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1963-01-18 | 1900-01-01 | ||
| USB421061I5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1964-12-24 | |||
| US3388009A (en) * | 1965-06-23 | 1968-06-11 | Ion Physics Corp | Method of forming a p-n junction by an ionic beam |
-
1968
- 1968-10-04 JP JP43071852A patent/JPS4915377B1/ja active Pending
-
1969
- 1969-09-30 US US00862438A patent/US3745070A/en not_active Expired - Lifetime
- 1969-10-02 GB GB1239684D patent/GB1239684A/en not_active Expired
- 1969-10-03 DE DE1950069A patent/DE1950069B2/de not_active Ceased
- 1969-10-03 FR FR6933855A patent/FR2023314A1/fr active Pending
- 1969-10-03 NL NL6914952A patent/NL6914952A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE1950069A1 (de) | 1970-04-23 |
| GB1239684A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1971-07-21 |
| FR2023314A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1970-08-21 |
| DE1950069B2 (de) | 1981-10-08 |
| NL6914952A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1970-04-07 |
| US3745070A (en) | 1973-07-10 |