JPS4410453Y1 - - Google Patents
Info
- Publication number
- JPS4410453Y1 JPS4410453Y1 JP4365566U JP4365566U JPS4410453Y1 JP S4410453 Y1 JPS4410453 Y1 JP S4410453Y1 JP 4365566 U JP4365566 U JP 4365566U JP 4365566 U JP4365566 U JP 4365566U JP S4410453 Y1 JPS4410453 Y1 JP S4410453Y1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4365566U JPS4410453Y1 (en) | 1966-05-11 | 1966-05-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4365566U JPS4410453Y1 (en) | 1966-05-11 | 1966-05-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS4410453Y1 true JPS4410453Y1 (en) | 1969-04-26 |
Family
ID=31778381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4365566U Expired JPS4410453Y1 (en) | 1966-05-11 | 1966-05-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS4410453Y1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240974A (en) * | 1975-09-27 | 1977-03-30 | Mitsubishi Electric Corp | Package for semiconductor chips |
-
1966
- 1966-05-11 JP JP4365566U patent/JPS4410453Y1/ja not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240974A (en) * | 1975-09-27 | 1977-03-30 | Mitsubishi Electric Corp | Package for semiconductor chips |