JPH1197561A - Non-volatile semiconductor storage and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the retention property of a non-volatile semiconductor storage by machining a stack gate electrode, enabling an insulating film to grow on the side wall of a floating gate due to thermal oxidation, by performing thermal nitriding for the side wall of the floating gate, and by forming an interlayer insulating film. SOLUTION: A tunnel oxide film 2 is formed on a silicon semiconductor substrate 1, a stack gate electrode where floating and control gates 4 and 6 are laminated on the tunnel oxide film 2 is machined, and a field oxide film 3 being used as an insulating film is allowed to grow on the side wall of the floating gate 4 by thermal oxidation. Then, thermal nitriding is performed for the side wall of the floating gate 4 and an interlayer insulating film 9 is formed via an oxide film 8, thus improving the retention property of a nonvolatile semiconductor storage and increasing the capacity of a semiconductor memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device by nitriding an interface between a sidewall of a floating gate and an interlayer insulating film.
The present invention relates to a technique for improving retention characteristics of a nonvolatile semiconductor memory device having a so-called Stacked Gate type structure.

[0002]

2. Description of the Related Art In recent years, in a semiconductor memory device, in particular, a nonvolatile semiconductor memory device, a threshold voltage (Vth) distribution of a transistor has been narrowed more and more with a reduction in cell size. If the Vth distributions overlap, the stored data cannot be read accurately, so that the Vths must not overlap, and the retention characteristics of the nonvolatile semiconductor memory device may be reduced. There is an increasing need for improvement.

In order to increase the capacity of a non-volatile semiconductor memory device, one bit (binary), that is, Vth, of a single memory transistor has been used in parallel with the conventional method of reducing the cell size. In order to increase the number of levels from two to four or more, a multi-value technology for storing two or more bits with a single memory transistor is being studied.

[0004] In order to realize such multi-valued conversion, FIG.
As shown in the figure, where two Vth distributions had to be contained within a certain voltage range, Vt
The h distribution must be accommodated, and accordingly, the difference between each Vth distribution becomes smaller.

[0005] For this reason, it is more susceptible to the influence of the disturb characteristic and the holding characteristic than in the past, and as shown in FIG. 18, when Vths overlap each other, the stored data can be read accurately. You can't do it.

Therefore, it is important to improve the retention characteristics of the memory transistor in order to increase the capacity and reduce the cell size of the nonvolatile semiconductor memory device.

Here, FIG. 19 is a cross-sectional view of a conventional nonvolatile semiconductor memory device having a plurality of gate electrodes in a stacked type, that is, a so-called Stacked Gate nonvolatile semiconductor memory device. In the figure, 1 is a silicon semiconductor substrate, 2 is a tunnel oxide film, 3 is a field oxide film, 4 is a floating gate, 5 is an inter-gate insulating film, 6 is a control gate, 7 is a diffusion layer, 8 is an oxide film, and 9 is Each shows an interlayer insulating film.

In this Stacked Gate type nonvolatile semiconductor memory device, Vth is changed according to the amount of charge stored in the floating gate 4 and is made to correspond to data.

That is, normally, when no voltage is applied to the control gate and the like, electrons in the floating gate are distributed along the inner wall of the floating gate as shown in FIG. 20, and at the time of reading, as shown in FIG. At the upper wall of the floating gate.

[0010]

However, FIG.
As shown in FIG. 2, in the case of a structure in which the side wall C of the floating gate is in direct contact with the insulating film, as in a conventional memory cell, electrons are trapped at the level of the interface over time. Will be lost.

When reading is performed in a state where electrons are captured in such an interface state, not all electrons are distributed on the upper wall of the floating gate as shown in FIG. Apparently, Vth seems to be lower than that in the case where it has not been captured. Due to this decrease in Vth, the distribution of Vth is widened, and as described above, there is a problem in promoting multi-valued data.

Further, as the memory cell size becomes smaller, the ratio of the floating gate side wall area to the floating gate surface area occupies a higher ratio. It becomes more noticeable.

As described above, when realizing a large capacity of a nonvolatile semiconductor memory device, the holding characteristic of a memory transistor is improved in order to realize a conventional reduction in cell size and multi-value. Is required.

The present invention has been made based on the above background, and has as its object to improve the retention characteristics of a nonvolatile semiconductor memory device.

[0015]

According to the present invention, there is provided a nonvolatile semiconductor memory device having a floating gate for storing electric charges on a semiconductor substrate and having a control gate thereover via an interlayer insulating film. Is a non-volatile semiconductor memory device in which the interface between the side wall and the interlayer insulating film is nitrided. The present invention also relates to a method for manufacturing a nonvolatile semiconductor memory device having a floating gate for accumulating charges on a semiconductor substrate and having a control gate on the floating gate via an interlayer insulating film. A step of growing an insulating film on the side wall of the floating gate, a step of performing thermal nitridation on at least the side wall of the floating gate, and a step of forming an interlayer insulating film. .

Hereinafter, the present invention will be described in detail.

The nonvolatile semiconductor memory device of the present invention has a structure (St) in which a floating gate 4 and a control gate 6 are stacked as shown in FIGS. 1 (a) and 1 (b).
ACKed gate structure). In the figure, 1 is a silicon semiconductor substrate, 2 is a tunnel oxide film, 3 is a field oxide film, 4 is a floating gate, 5 is an inter-gate insulating film, 6 is a control gate, 7 is a diffusion layer, 8 is an oxide film, 9 is Each shows an interlayer insulating film. The nonvolatile semiconductor memory device according to the present invention is characterized in that the interface between the side wall of the floating gate 4 and the interlayer insulating film 9 is nitrided.

The nitriding is performed, for example, by 1) Stacked.
After processing the Gate, an insulating film is grown on the side wall of the floating gate by thermal oxidation or chemical vapor deposition (CVD), and then, for example, rapid thermal nitridation (Rapid Thermal Nitr) in the presence of ammonia.
2) Stacked Gat
e, for example, CVD (Chemical V)
an insulating film is grown on the sidewalls of the floating gate by apor deposition, and thereafter, for example, rapid thermal nitridation is performed in the presence of ammonia, or 3) after processing the stacked gate, for example, N ₂ O, NO gas Thermal nitridation oxidation (R
TON) or the like.

In the nonvolatile semiconductor memory device of the present invention, since the interface between the floating gate side wall and the interlayer insulating film is nitrided, electrons are trapped on the floating gate side wall as in the conventional nonvolatile semiconductor memory device. There is no. Therefore, the shift of Vth caused by the capture of electrons on the side wall of the floating gate can be effectively suppressed.
That is, the reliability of the data is improved, and the difference between the respective Vth distributions can be set small. Therefore, a multi-valued semiconductor memory device can be easily realized, and the capacity of the semiconductor memory can be increased.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, after a gate electrode is processed, a step of growing an insulating film on a side wall of a floating gate by thermal oxidation, a step of performing thermal nitridation, and a step of forming an interlayer insulating film And a plurality of gate electrodes arranged in a stacked type.

More specifically, the nitriding method includes:
For example, the following two can be mentioned.

(1) After processing the stacked gate, an insulating film such as an oxide film or an ONO film is grown on the side wall of the floating gate by thermal oxidation, and then, for example, rapid thermal nitriding (Rapid) in the presence of ammonia
First, for example, a Stacked Gate is performed by the following procedure.
Perform processing.

For example, a wiring portion (field portion) of an LSI is formed on a p-type silicon semiconductor substrate by a selective oxidation technique.
A thick silicon oxide film, and then, for example, forming a floating gate in a memory cell portion.
The polycrystalline silicon of the layer is grown by, for example, a chemical vapor deposition method (CVD method). At this time, for example, the conductivity can be increased by doping impurities such as phosphorus at a high concentration. On top of that, thermal oxidation or CVD
Oxide film or ONO film (SiO ₂ / SiN /
(A laminated film of SiO ₂ ). After that, the control gate of the memory cell and 2 for forming the peripheral transistor are formed.
A layer of polycrystalline silicon or polycide is formed by, for example, a CVD method. The polycide film is formed of, for example, a laminated film including a silicide film such as tungsten silicide, molybdenum silicide, titanium silicide, or tantalum silicide, and a polysilicon film. Next, in a photo-etching step, polycrystalline silicon (or polycide) in the element forming portion is formed.
The gate processing is completed by removing all the film and the oxide insulating film.

Next, the gate portion is completely surrounded by the silicon oxide film by, for example, thermal oxidation. Then, for example, thermal annealing is performed in an atmosphere of ammonia gas for about 10 to 60 minutes. The annealing temperature is not particularly limited, but is preferably 800 to 1100 ° C. 800
If the temperature is lower than 1 ° C., the nitridation reaction progresses slowly, so that the effect of nitriding cannot be obtained. Is concerned.

The interface between the polysilicon forming the floating gate and the silicon oxide film as the upper layer is
There is a transition region that changes the structure in iO ₂ . In this transition region, there is a chemical bond called a dangling bond, which is not bonded to the second atom but comes out to the solid surface. It is considered that the electrons are captured on the sidewalls of the floating gate covered with the oxide film due to the presence of the dangling bonds, and the rapid thermal nitridation terminates the dangling bonds.
It is considered that the shift of Vth due to the trapping of electrons on the side wall of the floating gate can be suppressed.

(2) Method of Performing Rapid Thermal Nitriding Oxidation (RTON) in the Presence of N ₂ O and NO After Processing of Stacked Gate The Stacked Gate is processed in the same manner as described above. Then, in the presence of N ₂ O or NO gas, for 10 minutes to
In this method, thermal anneal is performed at 800 to 1100 ° C. for 60 minutes to form a nitrided oxide film on the sidewall of the floating gate.

Gases such as NO and N ₂ O used for this nitridation oxidation are pure NO and N ₂ O gas, as well as nitrogen,
Those diluted with argon or the like can also be used.

By performing such a process, dangling bonds existing at the interface between the floating gate and the oxide film can be terminated in the same manner as in the above (1), and electrons are captured on the side walls of the floating gate. Vth shift due to this can be suppressed.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a nonvolatile semiconductor memory device of the present invention, for example, a nonvolatile semiconductor memory device having a plurality of gate electrodes arranged in a stacked type, such as an EPROM, an E ² PROM or a flash type E ² PROM, is used. is there.

First Embodiment As a first embodiment of the present invention, an EPROM will be described as an example.

FIG. 2 is a sectional view of an n-channel type EPROM memory cell. This n-channel type memory cell has a control gate 15 and a floating gate 14.
The layer has a gate made of polysilicon. The first layer floating gate 14 is completely covered with a silicon oxide film, and is a gate for holding electrons injected by writing. The sidewall surface of the floating gate 14 is nitrided, and the dangling bond existing at the interface between the sidewall of the floating gate 14 and the upper silicon oxide film 12 is completely terminated. Therefore,
The structure is such that the Vth shift caused by the trapping of electrons on the side wall of the floating gate 14 can be suppressed.

The second-layer control gate 15 is connected to a word line selection decoder output (not shown).
It also serves as a cell selection transistor required for a p-channel type. Then, the whole is covered with an interlayer insulating film 12 and an aluminum wiring film 13 is formed through a contact hole.
Is connected. Diffusion layers 11 are provided on both sides of the gate electrode portion.

Writing to the memory is performed by applying a voltage to the drain 16 and injecting some of the electrons accelerated by the high electric field in the depletion layer region into the floating gate over the energy barrier of the oxide film. . In the state where electrons are injected, Vth shifts in the positive direction, so that the conduction state is established.
The information is stored as memory information corresponding to 0 ". The memory is erased by, for example, irradiating X-rays or ultraviolet rays.

The EPROM can be manufactured as follows.

That is, as shown in FIG. 3, a field oxide film 17 is formed on a p-type silicon semiconductor substrate 10 by a selective oxidation technique. Next, as shown in FIG. 4, after forming a gate oxide film by thermal oxidation, phosphorus as a first layer impurity for forming a floating gate of the memory cell portion (A) is doped in-situ. A crystalline silicon layer 18 is grown.

Next, as shown in FIG. 5, the SiO ₂ / Si
The inter-gate insulating film 19 made of N / SiO ₂ is CV
After the formation by the D method, as shown in FIG. 6, a WSi / PolySi laminated film 20 for forming a control gate is deposited by the CVD method.

Next, by thermal oxidation, as shown in FIG.
As shown in (b), after performing the etching process, an oxide film is formed on the surface of the transistor, and thermal annealing is performed at 900 ° C. for 10 minutes in an N ₂ O gas atmosphere. This process is performed.

Next, as shown in FIG. 7, a diffusion layer 26 and an interlayer insulating film 24 are formed, and a wiring layer 2 made of aluminum is formed.
By disposing 5, the EPROM can be manufactured.

The EPROM manufactured as described above is
The dangling bond existing at the interface between the floating gate side wall and the insulating film can be nitrided and terminated, so that electrons are not captured and Vth does not fluctuate.

Second Embodiment In the second embodiment of the present invention, an E ² PROM will be described as an example.

The E ² PROM is an electrically rewritable nonvolatile semiconductor memory device. FIG. 8 shows a cross-sectional view (only the memory transistor) of the E ² PROM. The figure shows FLOTOX (Floating Gate).
(Tunnel Oxide) structure. In the FLOTOX cell, a tunnel oxide film 31 having a small oxide film thickness is provided between the drain of the memory transistor and the floating gate. By tunneling electrons in the oxide film, electrons can be injected into the floating gate or removed from the floating gate. Erasing is performed by applying a high voltage of 15 to 20 V to the control gate, grounding the drain, and injecting electrons into the floating gate. In this case, a nitrided oxide film is formed on the side wall surface of the floating gate 30 by performing thermal annealing in the presence of N ₂ O, and the dangling oxide existing at the interface between the floating gate side wall and the insulating film is formed. The ring bond is nitrided and terminated. Therefore, electrons are not captured and Vth does not fluctuate.

The above E ² PROM can be manufactured as follows.

First, as shown in FIG. 9, phosphorus is ion-implanted into a p-type silicon semiconductor substrate 27 as an impurity to form an n-well, and a field oxide film 2 is formed by a selective oxidation technique.
By forming 8, element isolation is performed.

Next, as shown in FIG. 10, arsenic or phosphorus is implanted into the tunnel region of the memory transistor.
An n-layer is formed. Further, a tunnel oxide film 31 having a thickness of about 100 ° is formed in that portion by thermal oxidation.

Next, as shown in FIG. 11, a first polysilicon layer for forming a floating gate is deposited, and the floating gate 34 is formed by photoetching.
To form Next, as shown in FIG. 12, after removing the oxide film on the field of the peripheral circuit, a gate oxide film 35 of the MOS transistor is formed. At this time, the polysilicon layer on the floating gate in the memory cell portion is also oxidized, and an interlayer insulating film 35 is formed.

Next, as shown in FIG. 13, a second polysilicon layer for forming a control gate is deposited by, for example, a CVD method. Then, as shown in FIG. 14, the gate 37 of the MOS transistor is processed by photoetching. At this time, the memory cell portion is covered with a resist film. Next, the peripheral circuit portion is covered with a resist film, and a control gate and a word line of the memory cell portion are formed.

Next, as shown in FIG. 14, boron is introduced by ion implantation to form the source / drain 39 of the p-channel transistor, and arsenic is ion-implanted.
The source / drain 40 of the n-channel transistor is formed.

Finally, as shown in FIG. 15, a PSG (phosphor glass) film 41 is deposited, a contact hole is opened, and an aluminum wiring 42 is formed as shown in FIG.
By forming the passivation film 43, a target FLOTOX structure E ² PROM can be manufactured.

According to the present invention, there is provided a nonvolatile semiconductor memory device having a plurality of gate electrodes arranged in a stacked type, wherein an interface between a side wall of a floating gate and an interlayer insulating film is nitrided. A storage device and a method of manufacturing the same. Therefore, the present invention can be variously modified within the scope of the present invention, without any particular limitation, other than those specifically mentioned in the above description.

[0050]

As described above, according to the present invention,
Since the shift of Vth caused by the capture on the side wall of the floating gate can be suppressed, the retention characteristics (data reliability) of the nonvolatile semiconductor memory device can be improved. According to the present invention, since the shift of Vth can be effectively suppressed, the difference between the respective Vth distributions can be set small.

Therefore, it is possible to increase the number of values of the nonvolatile semiconductor memory device and increase the capacity of the memory.

[Brief description of the drawings]

FIG. 1A is an example of a nonvolatile semiconductor memory device of the present invention having a plurality of electrodes arranged in a stacked type (a). (B)
FIG. 3 is a cross-sectional view in a direction perpendicular to FIG.

FIG. 2 shows an n-channel type EP according to an embodiment of the present invention.
It is sectional drawing of ROM.

FIG. 3 is a view showing a process in which the EPROM shown in FIG. 2 is manufactured, in which a field oxide film is formed on a p-type semiconductor substrate.

FIG. 4 is a diagram illustrating a process in which the EPROM shown in FIG. 2 is being manufactured, in which a polycrystalline silicon layer 18 is deposited.

FIG. 5 is a view in the process of manufacturing the EPROM shown in FIG. 2, in which a laminated film 20 of WSi / PolySi is deposited.

FIG. 6 is a diagram showing the process of manufacturing the EPROM shown in FIG. 2, without performing a gate process, forming an oxide film on the surface of the transistor, and performing thermal annealing in the presence of N ₂ O gas; (A). (B) is an enlarged view of a floating gate and a control gate part.

FIG. 7 is a diagram illustrating a process in which the EPROM shown in FIG. 2 is manufactured, in which a diffusion layer 26, an interlayer insulating film 24, and an aluminum wiring layer 26 are provided.

FIG. 8 is a sectional view of an E ² PROM according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating the process of manufacturing the E ² PROM shown in FIG. 8, in which an n-well 32 and a field oxide film 28 are formed on a p-type semiconductor substrate 27;

FIG. 10 is a diagram illustrating a process in which the E ² PROM shown in FIG. 8 is being manufactured, in which a tunnel oxide film 31 is formed on an n-layer 33;

FIG. 11 is a view in the middle of manufacturing the E ² PROM shown in FIG. 8, in which a floating gate 34 is formed.

FIG. 12 is a diagram illustrating the process of manufacturing the E ² PROM shown in FIG. 8, in which a floating gate 34 is formed and a gate oxide film 35 is formed.

FIG. 13 is a diagram illustrating a process in which the E ² PROM shown in FIG. 8 is manufactured, in which a gate of a MOS transistor 37 is processed after a gate oxide film 35 is formed.

FIG. 14 is a diagram illustrating the process of manufacturing the E ² PROM shown in FIG. 8, in which after processing the gate of the MOS transistor 37, the source / drain 39 of the p-channel transistor;
And source / drain 40 of n-channel transistor
FIG.

FIG. 15 is a view in the middle of manufacturing the E ² PROM shown in FIG. 8, in which a PSG film 41 is deposited and then a contact hole is opened.

FIG. 16 is a diagram illustrating the process of manufacturing the E ² PROM shown in FIG. 8, in which an aluminum wiring 42 and a passivation film 43 are formed after opening a contact hole.

FIG. 17 is a conceptual diagram showing a Vth distribution of a nonvolatile semiconductor memory device having two Vth distribution levels.

FIG. 18 is a conceptual diagram showing a Vth distribution of a nonvolatile semiconductor memory device having four Vth distribution levels.

FIG. 19 is a cross-sectional view of a conventional nonvolatile semiconductor memory device. (B) is a sectional view in a direction perpendicular to (a).

FIG. 20 is a diagram showing a charge distribution of the floating gate 4 when no voltage is applied to the control gate 6 of the conventional nonvolatile semiconductor memory device.

FIG. 21 is a diagram showing a charge distribution of a floating gate 4 when a voltage is applied to a control gate 6 of a conventional nonvolatile semiconductor memory device.

FIG. 22 is a diagram showing a state in which electrons are captured at the level of the interface of the floating gate 4 of the conventional nonvolatile semiconductor memory device.

FIG. 23 shows a state in which electrons are captured at the interface level of the floating gate 4 of the conventional nonvolatile semiconductor memory device.
FIG. 3 is a diagram showing a state where a voltage is applied to a control gate 6.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon semiconductor substrate, 2, 31 ... Tunnel oxide film,
3, 17, 28 ... field oxide film, 4, 14, 21,
30, 34 ... floating gate, 5, 19, 35 ...
Inter-gate insulating film, 6, 15, 22, 36 ... control gate, 7, 11, 26, 32, 38 ... diffusion layer, 8 ... oxide film, 9, 12, 24 ... interlayer insulating film, 10, 27 ... p-type Silicon semiconductor substrate, 13, 25, 42: aluminum wiring film, 16: drain, 18: polycrystalline silicon layer, 2
0 ... Layer film of WSi / PolySi, 23 ... Gate electrode, 29, 33 ... N layer, 37 ... Gate of MSO transistor, 39 ... Source / drain of p-channel transistor, 40 ... Source / drain of n-channel transistor, 41 ... PSG film, 43 ... passivation film, A ...
Memory cell portion, B: peripheral transistor portion, C: sidewall of floating gate

Claims (10)

[Claims] 1. A nonvolatile semiconductor memory device having a floating gate for storing charges on a semiconductor substrate and having a control gate thereover via an interlayer insulating film, comprising: A non-volatile semiconductor memory device whose interface is nitrided. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile semiconductor memory device has three or more threshold voltage levels. 3. A method for manufacturing a nonvolatile semiconductor memory device having a floating gate for storing electric charges on a semiconductor substrate and having a control gate thereover via an interlayer insulating film, comprising the steps of: A method of growing an insulating film on at least a side wall of a floating gate, a step of performing thermal nitridation on at least a side wall of the floating gate, and a step of forming an interlayer insulating film. . 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein said insulating film is a silicon oxide film. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein said step of performing thermal nitriding is a step of heating to 800 to 1200 ° C. in the presence of ammonia. 6. A method of manufacturing a nonvolatile semiconductor memory device having a floating gate for storing charges on a semiconductor substrate and having a control gate on the floating gate via an interlayer insulating film. Forming an insulating film on the side wall of the floating gate by using the above method, performing a rapid thermal nitridation oxidation on at least the side wall of the floating gate, and forming an interlayer insulating film. Method. 7. The method according to claim 6, wherein said insulating film is a silicon oxide film. 8. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein said step of performing thermal nitridation oxidation is a step of heating to 800 to 1200 ° C. in the presence of N ₂ O or NO gas. 9. A method for manufacturing a nonvolatile semiconductor memory device having a plurality of gate electrodes arranged in a stacked type, wherein: a step of forming an insulating film on a semiconductor substrate; and a step of forming a floating gate on the insulating film. Forming an oxide film on the surface of the floating gate by thermal oxidation; performing thermal nitridation on at least a side wall of the floating gate; forming an interlayer insulating film; and forming a control gate A method for manufacturing a nonvolatile semiconductor memory device, comprising: 10. A method for manufacturing a nonvolatile semiconductor memory device having a plurality of gate electrodes arranged in a stacked type, wherein: a step of forming an insulating film on a semiconductor substrate; and a step of forming a floating gate on the insulating film. Forming an oxide film on the surface of the floating gate by thermal oxidation; performing rapid thermal nitridation and oxidation on at least the side wall of the floating gate; forming an interlayer insulating film; forming a control gate A method of manufacturing a nonvolatile semiconductor memory device.