JPH1167957A - Electronic component and manufacture of electronic component - Google Patents

Electronic component and manufacture of electronic component

Info

Publication number
JPH1167957A
JPH1167957A JP9222196A JP22219697A JPH1167957A JP H1167957 A JPH1167957 A JP H1167957A JP 9222196 A JP9222196 A JP 9222196A JP 22219697 A JP22219697 A JP 22219697A JP H1167957 A JPH1167957 A JP H1167957A
Authority
JP
Japan
Prior art keywords
gold
substrate
electrode
films
gold film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9222196A
Other languages
Japanese (ja)
Other versions
JP3454097B2 (en
Inventor
Hiroshi Haji
宏 土師
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22219697A priority Critical patent/JP3454097B2/en
Priority to US08/979,694 priority patent/US5909633A/en
Priority to KR1019970064578A priority patent/KR100272399B1/en
Publication of JPH1167957A publication Critical patent/JPH1167957A/en
Application granted granted Critical
Publication of JP3454097B2 publication Critical patent/JP3454097B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component, which can favorably bond gold wires on copper pads on the surface and the rear of a substrate and at the same time, can perform favorable soldering to electrodes. SOLUTION: Nickel films 22 and 25 are respectively formed on copper pads 21 on the surface of a substrate 11 and copper pads 24 on the rear of the substrate 11 and moreover, gold films 23 and 26 having a thickness of a full metallic bondability are respectively formed on the films 22 and the films 25. In order to inhibit the formation of a gold-tin compound, which impairs the reliability of soldering, the gold films 26 on electrodes 16 which are soldered, are removed by dry etching to form the electrodes 16 into a thin film. Thereby, since the amount of gold, which is dissolved in a solder is suppressed, solder bumps can be formed favorably. Moreover, as the gold films 23 have full thickness, the connection of the gold films 23 with a semiconductor element can be made favorably with a wire bonding or the like, and the reliability of an electronic component can be enhanced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、電子部品および電
子部品の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component and a method for manufacturing an electronic component.

【０００２】[0002]

【従来の技術】電子部品の組立て構造として、基板の表
面の電極上に基板と半導体素子を接続するためのワイヤ
をボンディングするとともに、他の電極上に突出電極で
あるバンプを形成するものが知られている。このような
電子部品としては、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒ
ｒａｙ）パッケージが知られている。ワイヤとしては金
ワイヤが多用されており、またバンプとしては半田が多
用されている。2. Description of the Related Art As an assembly structure of an electronic component, there is known an assembly structure in which a wire for connecting a substrate and a semiconductor element is bonded on an electrode on a surface of the substrate, and a bump which is a protruding electrode is formed on another electrode. Have been. Such electronic components include BGA (Ball Grid Ar)
ray) packages are known. Gold wire is frequently used as the wire, and solder is frequently used as the bump.

【０００３】図１０は従来の基板の断面図である。図
中、１はガラエポ基板などの基板であり、その上側と下
側の表面には回路パターンの銅電極２、３が形成されて
いる。また銅電極２、３上にはニッケル膜４、５が形成
されており、ニッケル膜４、５上には金膜６、７が形成
されている。そして上面側の銅電極２と下面側の銅電極
３は内部配線８で接続されている。一方の銅電極２の金
膜６上に基板１に搭載されたチップ（図外）を接続する
ための金ワイヤ９の先端をボンディングし、他方の銅電
極３の金膜７上に半田バンプ１０を形成して電子部品を
組み立てる。FIG. 10 is a sectional view of a conventional substrate. In the figure, reference numeral 1 denotes a substrate such as a glass epoxy substrate, and copper electrodes 2 and 3 of a circuit pattern are formed on the upper and lower surfaces thereof. Nickel films 4 and 5 are formed on the copper electrodes 2 and 3, and gold films 6 and 7 are formed on the nickel films 4 and 5. The copper electrode 2 on the upper surface and the copper electrode 3 on the lower surface are connected by an internal wiring 8. One end of a gold wire 9 for connecting a chip (not shown) mounted on the substrate 1 is bonded on the gold film 6 of one copper electrode 2, and a solder bump 10 is formed on the gold film 7 of the other copper electrode 3. To form an electronic component.

【０００４】ニッケル膜４、５や金膜６、７は一般にメ
ッキ法により形成される。金膜６、７は金ワイヤ９のボ
ンディング性を向上させるためのに形成されている。従
来、金膜６、７の厚さは０．２〜１ミクロン程度であっ
てかなり厚いものである。ニッケル膜４、５は銅電極
２、３の素材である銅が金膜６、７中へ拡散し、空気に
触れて酸化膜を生じるのを防ぐためのバリヤメタルとし
て形成されている。なお金膜６の表面に酸化膜が生じれ
ば、金ワイヤ９のボンディングが不良になる。The nickel films 4, 5 and the gold films 6, 7 are generally formed by a plating method. The gold films 6 and 7 are formed for improving the bonding property of the gold wire 9. Conventionally, the thickness of the gold films 6 and 7 is about 0.2 to 1 μm, which is quite thick. The nickel films 4 and 5 are formed as barrier metals for preventing copper as a material of the copper electrodes 2 and 3 from diffusing into the gold films 6 and 7 and coming into contact with air to form an oxide film. If an oxide film is formed on the surface of the gold film 6, the bonding of the gold wire 9 becomes defective.

【０００５】[0005]

【発明が解決しようとする課題】上記従来の方法では金
を電解メッキするときにバリアメタルであるニッケル膜
４，５の成分のニッケルがメッキ液に溶け込みこのニッ
ケルが金メッキに混入する。混入したニッケルのうち金
膜６、７の表面に位置するものは、チップを固定する工
程で加熱により酸化膜を形成する。この酸化膜は金ワイ
ヤ９のボンディングを阻害する。金膜が厚くなるほどそ
の表面のニッケルは少なくなるので、できるだけこの酸
化膜が形成されないように金膜６，７の厚さはある程度
以上に厚くする必要がある。In the above-mentioned conventional method, when electroplating gold, nickel, which is a component of the nickel films 4 and 5 as a barrier metal, dissolves in the plating solution and this nickel is mixed into the gold plating. Of the mixed nickel, those located on the surfaces of the gold films 6 and 7 form an oxide film by heating in the step of fixing the chip. This oxide film hinders bonding of the gold wire 9. Since the nickel on the surface decreases as the thickness of the gold film increases, the thickness of the gold films 6 and 7 needs to be increased to a certain degree or more so that the oxide film is not formed as much as possible.

【０００６】しかしながら金膜６，７を厚くすると半田
バンプ１０のボンディング力を低下させる。何故なら
ば、半田バンプ１０を形成する際には、金膜７中の金は
半田バンプ１０中へ溶解して半田中のスズと脆い化合物
を形成するからである。このように金ワイヤ９のボンデ
ィングのためには一方の金膜６は厚い方がよく、これに
対し半田バンプ１０の形成などの半田付けに際しては他
方の金膜７は薄い方がよく、すなわち両者を同時に満足
することができず背反関係にあるという問題点があっ
た。However, when the gold films 6 and 7 are made thicker, the bonding force of the solder bump 10 is reduced. This is because, when the solder bumps 10 are formed, the gold in the gold film 7 dissolves into the solder bumps 10 to form a brittle compound with tin in the solder. As described above, it is better that one gold film 6 is thicker for bonding the gold wire 9, whereas it is better that the other gold film 7 is thinner for soldering such as formation of the solder bumps 10, ie, both Cannot be satisfied at the same time, and there is a problem that they are in conflict.

【０００７】そこで本発明は、基板の電極上に、金ワイ
ヤを良好にボンディングできるとともに、半田付けを良
好に行える電子部品の製造方法を提供することを目的と
する。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an electronic component which can bond a gold wire to an electrode of a substrate satisfactorily and can perform a good soldering.

【０００８】[0008]

【課題を解決するための手段】請求項１記載の電子部品
は、銅の表面に少なくともニッケルを含むバリヤメタル
が形成された基板と、前記バリヤメタル上に金属接合性
が十分な厚みを以て形成された金膜と、前記基板上に搭
載された半導体素子と、この半導体素子と前記金膜を接
続する接続手段とを備え、前記金膜を薄膜化した電極上
に半田付け部を有する。According to the present invention, there is provided an electronic component comprising: a substrate having a barrier metal containing at least nickel formed on a copper surface; and a metal having a sufficient metal bonding property formed on the barrier metal. The semiconductor device includes a film, a semiconductor element mounted on the substrate, and connection means for connecting the semiconductor element and the gold film, and has a soldering portion on an electrode having the gold film thinned.

【０００９】請求項２記載の電子部品の製造方法は、銅
の表面に少なくともニッケルを含むバリヤメタルを形成
する工程と、このバリヤメタル上に金属接合性が十分な
厚みの金膜を形成する工程と、半導体素子を前記基板上
に搭載する工程と、この半導体素子を前記金膜に接続す
る工程と、前記半導体素子を樹脂封止する工程と、樹脂
封止後に前記金膜をドライエッチングにより薄膜化する
工程と、前記金膜を薄膜化した電極上に半田付けを行う
工程とを含む。According to a second aspect of the present invention, there is provided a method of manufacturing an electronic component, comprising: forming a barrier metal containing at least nickel on a surface of copper; and forming a gold film having a sufficient metal bondability on the barrier metal. Mounting a semiconductor element on the substrate, connecting the semiconductor element to the gold film, sealing the semiconductor element with a resin, and thinning the gold film by dry etching after the resin sealing. And a step of soldering the electrode on which the gold film is thinned.

【００１０】[0010]

【発明の実施の形態】上記構成の本発明によれば、基板
の電極上に金属接合性が十分な厚みの金膜を形成した後
に半田の接合性を阻害する金膜をプラズマクリーニング
により除去して薄くした後に半田バンプの形成を行うこ
とにより、ワイヤボンディングなどによる金膜と半導体
素子との接続が良好に行えるとともに、半田バンプを良
好に形成できる。According to the present invention having the above structure, a gold film having a sufficient metal bonding property is formed on an electrode of a substrate, and then the gold film which inhibits the bonding property of the solder is removed by plasma cleaning. By forming the solder bumps after thinning, the connection between the gold film and the semiconductor element by wire bonding or the like can be performed well, and the solder bumps can be formed well.

【００１１】以下、本発明の実施の形態を図面を参照し
て説明する。図１は本発明の一実施の形態の電子部品の
組立構造図、図２、図３は同基板の断面図、図４は同基
板の部分断面図、図５、図６は同基板の断面図、図７は
同ドライエッチング装置の断面図、図８、図９は同基板
の断面図である。An embodiment of the present invention will be described below with reference to the drawings. 1 is an assembly structure diagram of an electronic component according to an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views of the same board, FIG. 4 is a partial cross-sectional view of the same board, and FIGS. 5 and 6 are cross-sectional views of the same board. 7 and 8 are cross-sectional views of the same dry etching apparatus, and FIGS. 8 and 9 are cross-sectional views of the same substrate.

【００１２】まず電子部品Ａの構造について説明する。
図１において、１１は基板であり、基板１１の上面には
チップ１２が熱硬化型接着剤３１でボンディングされて
いる。チップ１２の表面の電極１３と基板上面の電極１
４とは金ワイヤ１５で電気的に接続されている。１５’
は金ワイヤの先端部に形成された金ボールであり、この
金ボール１５’が電極１３にボンディングされている。First, the structure of the electronic component A will be described.
In FIG. 1, reference numeral 11 denotes a substrate, and a chip 12 is bonded to the upper surface of the substrate 11 with a thermosetting adhesive 31. The electrode 13 on the surface of the chip 12 and the electrode 1 on the upper surface of the substrate
4 is electrically connected with the gold wire 15. 15 '
Is a gold ball formed at the tip of the gold wire, and the gold ball 15 ′ is bonded to the electrode 13.

【００１３】基板１１の下面には、電極１６が形成され
ている。電極１６上には半田バンプ１７が形成されてい
る。電極１４と電極１６は内部配線１８で接続されてい
る。基板１１の上面はチップ１２や金ワイヤ１５を封止
するため樹脂モールド１９が形成されている。An electrode 16 is formed on the lower surface of the substrate 11. A solder bump 17 is formed on the electrode 16. The electrodes 14 and 16 are connected by an internal wiring 18. A resin mold 19 is formed on the upper surface of the substrate 11 to seal the chip 12 and the gold wire 15.

【００１４】次に図２〜図８を参照して図１に示す電子
部品の製造方法を説明する。なお図２〜図８は製造工程
順に示している。まず、図２に示すように、基板１１の
上面側に電極１４が形成される。電極１４は銅電極２１
上にバリアメタル層としてニッケル膜２２をコーティン
グして形成し、更にニッケル膜２２の上に金膜２３が金
属接合性が十分な厚み、すなわち金属とのボンディング
を阻害しないために十分な厚み（０．２〜１ミクロン程
度）を以て形成されたものである。銅電極２１は基板１
１の表面に銅箔を貼り付け、不要な部分をエッチングに
より除去して形成される。また、ニッケル膜２２および
金膜２３はメッキによって形成される。また下面側にも
電極１６が同様に形成される。電極１６は銅電極２４上
にニッケル膜２５をコーティングし、更にニッケル膜２
５の上に金膜２６が上面側の電極１４と同様に形成され
る。Next, a method of manufacturing the electronic component shown in FIG. 1 will be described with reference to FIGS. 2 to 8 are shown in the order of the manufacturing process. First, as shown in FIG. 2, the electrode 14 is formed on the upper surface side of the substrate 11. The electrode 14 is a copper electrode 21
A nickel film 22 is coated thereon as a barrier metal layer, and a gold film 23 is formed on the nickel film 22 with a sufficient thickness for metal bonding, that is, a sufficient thickness (0) so as not to hinder bonding with metal. (Approximately .2 to 1 micron). Copper electrode 21 is substrate 1
1 is formed by attaching a copper foil to the surface and removing unnecessary portions by etching. The nickel film 22 and the gold film 23 are formed by plating. The electrode 16 is similarly formed on the lower surface side. The electrode 16 is formed by coating a nickel film 25 on a copper electrode 24,
5, a gold film 26 is formed in the same manner as the electrode 14 on the upper surface.

【００１５】次に、図３に示すように基板１１の上面に
半導体素子であるチップ１２が搭載される。チップ１２
は基板１１の上面に予め塗布された熱硬化型接着剤３１
によって接着され、その後基板１１は熱処理される。熱
硬化型接着剤３１が硬化することによりチップ１２は基
板１１に固定される。図４はこの熱処理後の基板１１の
電極１４、１６付近の断面図である。ここで金膜２３，
２６は金属接合性に十分な厚みを有しているため、金ワ
イヤのボンディング性を阻害するニッケルの酸化膜は金
膜２３，２６の表面には生じない。Next, as shown in FIG. 3, a chip 12 as a semiconductor element is mounted on the upper surface of the substrate 11. Chip 12
Is a thermosetting adhesive 31 previously applied to the upper surface of the substrate 11
Then, the substrate 11 is heat-treated. The chip 12 is fixed to the substrate 11 by curing the thermosetting adhesive 31. FIG. 4 is a sectional view of the vicinity of the electrodes 14 and 16 of the substrate 11 after the heat treatment. Here, the gold film 23,
Since 26 has a sufficient thickness for metal bonding, no nickel oxide film that inhibits the bonding property of the gold wire is formed on the surfaces of the gold films 23 and 26.

【００１６】次に図５に示すようにワイヤボンディング
により金ワイヤ１５を上面側の電極１４の金膜２３上に
ボンディングする。これにより、チップ１２は金膜２３
に接続される。したがって、金ワイヤ１５はチップ１２
と金膜２３とを接続する接続手段となっている。このと
き金膜２３の表面には金ワイヤのボンディング性を阻害
するニッケルの酸化膜がほとんどないため、良好なボン
ディングを行うことができる。この後、図６に示すよう
に樹脂モールド１９によるチップ１２および金ワイヤ１
５の封止が行われる。Next, as shown in FIG. 5, a gold wire 15 is bonded to the gold film 23 of the electrode 14 on the upper surface by wire bonding. As a result, the chip 12 becomes the gold film 23
Connected to. Therefore, the gold wire 15 is connected to the chip 12
And a gold film 23. At this time, since there is almost no nickel oxide film on the surface of the gold film 23 that hinders the bonding property of the gold wire, good bonding can be performed. Thereafter, as shown in FIG. 6, the chip 12 and the gold wire 1 by the resin mold 19 are formed.
5 is performed.

【００１７】次に電極１６側の金膜を薄くするために、
ドライエッチングが行われる。以下図７を参照してこの
ドライエッチングに用いられるドライエッチング装置４
０の構造を説明する。図７において、４１は上部ケーシ
ングである。上部ケーシング４１は下部ケーシング４２
とともに開閉可能な真空容器４３を形成する。下部ケー
シング４２の底部には電極４４が配設されている。電極
４４には高周波電源装置４５が接続されている。下部ケ
ーシング４２の底面にはパイプ４６，４７，４８が設け
られている。パイプ４６には真空源４９が接続されてい
る。またパイプ４７にはアルゴンガスなどのプラズマエ
ッチング用のガスを供給するガス供給部５０が接続され
ている。またパイプ４８には真空破壊用の弁５１が接続
されている。Next, in order to thin the gold film on the electrode 16 side,
Dry etching is performed. Referring to FIG. 7, a dry etching apparatus 4 used for this dry etching will be described below.
The structure of 0 will be described. In FIG. 7, reference numeral 41 denotes an upper casing. The upper casing 41 is a lower casing 42
And a vacuum container 43 that can be opened and closed. An electrode 44 is provided on the bottom of the lower casing 42. A high frequency power supply 45 is connected to the electrode 44. Pipes 46, 47, 48 are provided on the bottom surface of the lower casing 42. A vacuum source 49 is connected to the pipe 46. Further, a gas supply unit 50 for supplying a gas for plasma etching such as argon gas is connected to the pipe 47. Further, a valve 51 for vacuum break is connected to the pipe 48.

【００１８】上部ケーシング４１の上部にはアース電極
５２が装着されている。アース電極５２は接地部５３に
接地され、電極４４と対置されている。電極４４上には
基板１１が載置される。A ground electrode 52 is mounted on an upper portion of the upper casing 41. The ground electrode 52 is grounded to the ground 53 and is opposed to the electrode 44. The substrate 11 is placed on the electrode 44.

【００１９】このプラズマエッチング装置４０は上記の
ような構成より成り、以下その動作を説明する。図７に
示すように、基板１１を反転し電極１６側を上向きにし
て電極４４上に載置した状態で上部ケーシング４１が閉
じられる。次に真空源４９が真空吸引を開始し、真空容
器４３内部が所定の真空度に到達する。次にガス供給装
置５０よりアルゴンガスが真空容器４３内部に供給され
るとともに、電極４４には高周波電源装置４５により高
周波電圧が印加される。真空容器４３内部のアルゴンガ
スはプラズマ状態のアルゴンイオンとなり、図７におい
て破線矢印で示すように電極４４上に載置された基板１
１の上面に衝突してエッチングする。このようにして電
極１６表面の金膜２６が除去され、金膜２６は厚さ０．
０１〜０．２ミクロン程度に薄膜化される。金膜２６を
完全に除去しないのは、溶融した半田と電極１６とのぬ
れ性を良好に保つためである。The plasma etching apparatus 40 has the above-described configuration, and its operation will be described below. As shown in FIG. 7, the upper casing 41 is closed in a state where the substrate 11 is placed on the electrode 44 with the electrode 16 side turned upside down. Next, the vacuum source 49 starts vacuum suction, and the inside of the vacuum container 43 reaches a predetermined degree of vacuum. Next, an argon gas is supplied from the gas supply device 50 into the vacuum vessel 43, and a high-frequency voltage is applied to the electrode 44 by the high-frequency power supply 45. The argon gas in the vacuum chamber 43 becomes argon ions in a plasma state, and the substrate 1 mounted on the electrode 44 as shown by a broken arrow in FIG.
1 and collides with the upper surface. Thus, the gold film 26 on the surface of the electrode 16 is removed, and the gold film 26 has a thickness of 0.1 mm.
The thickness is reduced to about 01 to 0.2 microns. The reason why the gold film 26 is not completely removed is to maintain good wettability between the molten solder and the electrode 16.

【００２０】次に図８に示すように、電極１６側の金膜
２６上に半田ボール１７が搭載される。このとき、半田
ボール１７と金膜２６の間にはフラックス２０が塗布さ
れる。この後基板１１はリフロー工程に送られ、半田ボ
ール１７は電極１６面に半田付けされ、半田付け部とし
ての半田バンプ１７となって図１に示す電子部品Ａは完
成する。このとき金膜２６は半田バンプ１７中に溶解す
るが、金膜２６はドライエッチングにより薄膜化されて
いるため半田バンプ１７中に溶解する金の量はきわめて
少量である。したがって半田バンプ１７のボンディング
性を悪化させる金とスズの化合物の形成はわずかであ
り、信頼性の高い半田バンプ１７が形成される。また、
金膜２６の表面はエッチング処理されるため、半田のぬ
れ性を阻害するニッケルや汚染物等もきれいに取り除か
れている。したがって半田を電極にぬれ性よく接合させ
ることができる。Next, as shown in FIG. 8, a solder ball 17 is mounted on the gold film 26 on the electrode 16 side. At this time, the flux 20 is applied between the solder ball 17 and the gold film 26. Thereafter, the substrate 11 is sent to a reflow process, and the solder balls 17 are soldered to the surfaces of the electrodes 16 to become solder bumps 17 as soldered portions, thereby completing the electronic component A shown in FIG. At this time, the gold film 26 dissolves in the solder bump 17, but since the gold film 26 is thinned by dry etching, the amount of gold dissolved in the solder bump 17 is extremely small. Therefore, the formation of the compound of gold and tin that deteriorates the bonding property of the solder bump 17 is slight, and the solder bump 17 with high reliability is formed. Also,
Since the surface of the gold film 26 is etched, nickel, contaminants, and the like, which hinder the wettability of the solder, are also cleanly removed. Therefore, the solder can be bonded to the electrodes with good wettability.

【００２１】本発明は上記実施の形態に限定されないの
であって、上記実施の形態ではワイヤボンディングによ
り半導体素子を電極１４の金膜２３に接続する例を示し
ているが、接続の方法はこれに限定されず、リボンボン
ディング、ＴＡＢボンディング、フリップチップボンデ
ィングなどによるものであってもよい。The present invention is not limited to the above embodiment. In the above embodiment, an example is shown in which a semiconductor element is connected to the gold film 23 of the electrode 14 by wire bonding. The present invention is not limited thereto, and may be a method using ribbon bonding, TAB bonding, flip chip bonding, or the like.

【００２２】また、上記実施の形態では基板１１の一方
側に半導体素子が搭載され、他方の側に半田バンプが形
成される例を示しているが、要はボンディングと半田付
けが同一の基板内に混在する形態であればよい。例えば
図９（ａ）に示すように、基板４１に半導体素子４２を
搭載してワイヤボンディングにより基板４１の電極と接
続し、この同一面に形成された電極４４上の金膜を薄膜
化した後に電子部品４５を半田付けにより実装する形態
であってもよく、更に図９（ｂ）に示すように基板４６
の電極４７に半導体素子４８をワイヤボンディングによ
り接続し、同一面に形成された電極４９上の金膜を薄膜
化した後に半田バンプ５０を形成する形態であってもよ
い。Also, in the above embodiment, an example is shown in which a semiconductor element is mounted on one side of the substrate 11 and a solder bump is formed on the other side. Any form may be used as long as it is mixed with For example, as shown in FIG. 9A, a semiconductor element 42 is mounted on a substrate 41, connected to an electrode of the substrate 41 by wire bonding, and the gold film on the electrode 44 formed on the same surface is thinned. The electronic component 45 may be mounted by soldering. Further, as shown in FIG.
The semiconductor element 48 may be connected to the electrode 47 by wire bonding, the gold film on the electrode 49 formed on the same surface may be thinned, and then the solder bump 50 may be formed.

【００２３】[0023]

【発明の効果】本発明は、基板の電極上に金属接合性が
十分な厚みの金膜を形成した後に半田の接合性を阻害す
る金膜をドライエッチングにより除去して薄くした後に
半田バンプなどの半田付けを行うようにしているので、
ワイヤボンディングなどによる金膜と半導体素子との接
続に対してはボンディングを妨げるニッケルの酸化膜が
なく良好なボンディングを行えるとともに、半田付けに
対してはスズと金の脆弱な化合物の生成がなく良好な半
田付けを行うことができ、したがって信頼性の高い電子
部品を得ることができる。According to the present invention, after a gold film having a sufficient metal bondability is formed on an electrode of a substrate, the gold film which inhibits the bondability of the solder is removed by dry etching and thinned, and then a solder bump or the like is formed. So that the soldering of
For the connection between the gold film and the semiconductor element by wire bonding, etc., there is no nickel oxide film that hinders the bonding, and good bonding can be performed, and for soldering, there is no formation of fragile compounds of tin and gold. Soldering can be performed, and a highly reliable electronic component can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態の電子部品の組立構造図FIG. 1 is an assembly structure diagram of an electronic component according to an embodiment of the present invention.

【図２】本発明の一実施の形態の基板の断面図FIG. 2 is a sectional view of a substrate according to an embodiment of the present invention.

【図３】本発明の一実施の形態の基板の断面図FIG. 3 is a sectional view of a substrate according to an embodiment of the present invention.

【図４】本発明の一実施の形態の基板の部分断面図FIG. 4 is a partial cross-sectional view of a substrate according to an embodiment of the present invention.

【図５】本発明の一実施の形態の基板の断面図FIG. 5 is a sectional view of a substrate according to an embodiment of the present invention.

【図６】本発明の一実施の形態の基板の断面図FIG. 6 is a sectional view of a substrate according to an embodiment of the present invention.

【図７】本発明の一実施の形態のドライエッチング装置
の断面図FIG. 7 is a sectional view of a dry etching apparatus according to an embodiment of the present invention.

【図８】本発明の一実施の形態の基板の断面図FIG. 8 is a sectional view of a substrate according to an embodiment of the present invention.

【図９】本発明の一実施の形態の基板の断面図FIG. 9 is a cross-sectional view of a substrate according to an embodiment of the present invention.

【図１０】従来の基板の断面図FIG. 10 is a sectional view of a conventional substrate.

【符号の説明】[Explanation of symbols]

１１ 基板 １２ チップ １４、１６ 電極 １５ ワイヤ １７ 半田バンプ ２３、２６ 金膜 DESCRIPTION OF SYMBOLS 11 Substrate 12 Chip 14 and 16 Electrode 15 Wire 17 Solder bump 23 and 26 Gold film

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】銅の表面に少なくともニッケルを含むバリ
ヤメタルが形成された基板と、前記バリヤメタル上に金
属接合性が十分な厚みを以て形成された金膜と、前記基
板上に搭載された半導体素子と、この半導体素子と前記
金膜を接続する接続手段とを備え、前記金膜を薄膜化し
た電極上に半田付け部を有することを特徴とする電子部
品。A substrate on which a barrier metal containing at least nickel is formed on the surface of copper; a gold film formed on the barrier metal with a sufficient metal bonding property; and a semiconductor element mounted on the substrate. An electronic component, comprising: a connecting means for connecting the semiconductor element to the gold film; and a soldering portion on an electrode having the gold film thinned. 【請求項２】銅の表面に少なくともニッケルを含むバリ
ヤメタルを形成する工程と、このバリヤメタル上に金属
接合性が十分な厚みの金膜を形成する工程と、半導体素
子を前記基板上に搭載する工程と、この半導体素子を前
記金膜に接続する工程と、前記半導体素子を樹脂封止す
る工程と、樹脂封止後に前記金膜をドライエッチングに
より薄膜化する工程と、前記金膜を薄膜化した電極上に
半田付けを行う工程とを含むことを特徴とする電子部品
の製造方法。2. A step of forming a barrier metal containing at least nickel on a surface of copper, a step of forming a gold film having a sufficient metal bonding property on the barrier metal, and a step of mounting a semiconductor element on the substrate. Connecting the semiconductor element to the gold film, sealing the semiconductor element with a resin, thinning the gold film by dry etching after the resin sealing, and thinning the gold film. Performing a soldering process on the electrode.
JP22219697A 1996-11-29 1997-08-19 Electronic component and method of manufacturing electronic component Expired - Fee Related JP3454097B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP22219697A JP3454097B2 (en) 1997-08-19 1997-08-19 Electronic component and method of manufacturing electronic component
US08/979,694 US5909633A (en) 1996-11-29 1997-11-26 Method of manufacturing an electronic component
KR1019970064578A KR100272399B1 (en) 1996-11-29 1997-11-29 Method of manufacturing an electronic component and an electronic component manufactured thereby

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22219697A JP3454097B2 (en) 1997-08-19 1997-08-19 Electronic component and method of manufacturing electronic component

Publications (2)

Publication Number Publication Date
JPH1167957A true JPH1167957A (en) 1999-03-09
JP3454097B2 JP3454097B2 (en) 2003-10-06

Family

ID=16778658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22219697A Expired - Fee Related JP3454097B2 (en) 1996-11-29 1997-08-19 Electronic component and method of manufacturing electronic component

Country Status (1)

Country Link
JP (1) JP3454097B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001050517A1 (en) * 2000-01-04 2001-07-12 Multek Hong Kong Limited Semiconductor package and enhanced fbg manufacturing
US6998714B2 (en) 1999-08-25 2006-02-14 Micron Technology, Inc. Selectively coating bond pads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6998714B2 (en) 1999-08-25 2006-02-14 Micron Technology, Inc. Selectively coating bond pads
WO2001050517A1 (en) * 2000-01-04 2001-07-12 Multek Hong Kong Limited Semiconductor package and enhanced fbg manufacturing

Also Published As

Publication number Publication date
JP3454097B2 (en) 2003-10-06

Similar Documents

Publication Publication Date Title
US5909633A (en) Method of manufacturing an electronic component
US7250355B2 (en) Multilayered circuit substrate, semiconductor device and method of producing same
US7374969B2 (en) Semiconductor package with conductive molding compound and manufacturing method thereof
JPH06302604A (en) Resin-sealed semiconductor package and fabrication thereof
US20030001253A1 (en) Semiconductor device
US7221058B2 (en) Substrate for mounting semiconductor chip, mounting structure of semiconductor chip, and mounting method of semiconductor chip
JP2004363573A (en) Semiconductor chip mounted body and its manufacturing method
JP2000277649A (en) Semiconductor and manufacture of the same
JPH10275826A (en) Semiconductor device and manufacture thereof
US6699780B1 (en) Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching
JP2004119773A (en) Semiconductor device and its manufacturing method
US6537851B1 (en) Method of connecting a bumped compliant conductive trace to a semiconductor chip
JP3454097B2 (en) Electronic component and method of manufacturing electronic component
JP4440494B2 (en) Manufacturing method of semiconductor device
JPH10163241A (en) Manufacture of electronic component
JP2682496B2 (en) Flexible film and semiconductor device
JPH0831871A (en) Interface sealing film used for surface mount electronic device and surface mount structure
JP2002083901A (en) Electronic component
JPH1074859A (en) Qfn semiconductor package
JP2003179094A (en) Electronic component and method of manufacturing the same
JP3277830B2 (en) How to assemble electronic components
JP2000195887A (en) Electronic component
JP2001185642A (en) Package substrate for mounting semiconductor
JPH11251477A (en) Semiconductor package, semiconductor device, and their manufacturing method
KR20020057670A (en) Semiconductor chip package and manufacturing method the same

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070725

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080725

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090725

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090725

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100725

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120725

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120725

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130725

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees