JPH1151698A - Encoder inserter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an encoder inserter which can be split highly and relatively easily without sacrifice of the real time performance and without changing the circuit scale. SOLUTION: Analog phase A signal and phase B signal outputted from an encoder 1 are inputted, along with follow-up signals C, D of a memory element 8, to multipliers 2a, 2b and the outputs therefrom are added or subtracted by an adder/subtractor 3 before being inputted to comparators 4a, 4b. The comparators 4a, 4b generate two pulses, i.e., up pulse and down pulse, corresponding to the variation of the phase A signal and phase B signal. These pulses are counted by an up/down counter 7 and inputted to the addresses of ROM 8a, 8b in the memory element 8 storing sine and cosine data tables for the phase. The sine and cosine data are then read out and inputted as follow-up signals C, D, respectively, to the multipliers 2a, 2b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder interpolating device for detecting a length or an angle.

[0002]

2. Description of the Related Art Hitherto, several methods have been proposed to increase the resolution of length and angle measurement. For example, Japanese Patent Publication No. 7-94989 discloses that a sine wave signal is A
An example of a technique is disclosed in which digital conversion is performed by / D and position information inside a memory cell is read using the digital conversion as an address.
Normally, when the resolution is increased, it is necessary to increase the address space of the memory cells in proportion. However, here, means for reducing the address space to one-eighth is specified.

Further, Japanese Patent Application Laid-Open No. 5-43019, which is an earlier application filed by the present applicant, discloses an interpolation device that generates an internal phase and tracks the actual phase. According to the device disclosed in Japanese Utility Model Laid-Open No. 5-43019, an interpolation device that is resistant to noise and has good real-time properties required when incorporated in a servo system can be realized.

[0004]

However, in any case, the address space of the storage element is required as the resolution becomes higher. For example, considering a 16-bit address ROM that is commonly used, the resolution of a sine wave signal is 8
It is a bit, and even if it is reduced to one-eighth, the limit is about 10 bits, and there is a problem that the resolution cannot be increased due to the limitation of the element.

FIG. 5 is a schematic view of a storage device having 256 storage cells disclosed in Japanese Patent Publication No. 7-94989. This memory Z has a value of 0 in the coordinate direction XY.
It consists of a number of storage cells occupying a range of 15 decimal values. And these 256 storage cells are 360 °
Has 256 data words required for one division period or the full interpolation of a given signal period T, any of which can be selected via the address of the storage cell. In this case, the address is represented as a 4-bit word-length binary code by the attached coordinates X and Y.

[0006] As shown, the storage unit Z is divided into 16 sections which are distinguished by numerals 0 to 15. These sections are represented by four bits of a code, and an angle within one signal cycle corresponding to the graduation cycle T is given.

In recent years, it has been required that the measurement resolution be higher. For example, assuming that the number of divisions of the storage unit Z is 1000 as shown in FIG. 5, the resolution of the sine wave signal in consideration of the S / N needs to be 10 bits or more. That is, the address space of the ROM needs to be 20 bits or more, and even if the number of divisions is further increased, the address space of the ROM is limited, and it is difficult to realize.

On the other hand, there are many cases where real-time measurement is required, such as a device constituting a servo system or a device which takes in measurement data by applying a trigger. However,
As described above, when trying to increase the resolution, the ROM cannot be used due to the limitation of the address space and the like.

For this reason, for example, if the A / D data is read by a CPU and processed by a program, the resolution can be increased. However, since the processing time of the program is added, it takes much time. Therefore, the real-time property is impaired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an encoder interpolating apparatus which can easily achieve high division and can perform high-speed interpolation.

[0011]

That is, the present invention provides an encoder which outputs signals which can be converted into distances having phases different from each other by 90 degrees according to length or angle, and a follower signal to be generated and the above-mentioned distance. First and second multipliers for multiplying by a convertible signal, an adder / subtractor for adding / subtracting the outputs of the first and second multipliers, and a first and a second threshold value for the output of the adder / subtractor And first and second comparators that output first and second state signals in accordance with the comparison result, and first and second state signals that are output from the first and second comparators. And a storage element in which the following signal corresponding to the count value of the counter is stored, and the storage element is positioned based on the count value of the counter. Divided into a predetermined section of the angular rotated 360 °, and to store the sine and cosine data for the address.

In the encoder interpolating apparatus according to the first aspect, an analog sine wave signal (A-phase signal) which is a signal which can be converted into a distance different from each other by 90 degrees according to the length or angle output by the encoder. The signal and the B-phase signal) and the digital output (follow-up signal C and follow-up signal D) of the storage element are input to the first and second multipliers and multiplied. After the outputs of the two multipliers are added or subtracted by the adder / subtractor, the outputs are input to the first and second comparators.
The comparator generates two pulses corresponding to a change in the sine wave signal, that is, an up pulse and a down pulse, and these pulses are input to a counter and counted. For the phase output from this counter, the sine data and cosine data are read according to the address of the storage element in which the sine data and cosine data table is stored. These sine data and cosine data are used as a follow-up signal C and a follow-up signal D, and are input to the first and second multipliers, respectively.

In the encoder insertion device according to the second aspect, the amplitude of the sine wave signal obtained by the arithmetic unit is input to the level setting means, and the comparator level of the comparator is changed according to the amplitude. Controlled.

In the encoder interpolation device according to the third aspect, the amplitude of the sine wave signal obtained by the arithmetic unit is input to the gain setting means. By this gain setting means, a gain at which the amplitude is always at a predetermined level is calculated, and this is set by the gain control amplifier.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the encoder interpolation device of the present invention.

In FIG. 1, a sine wave signal (A-phase signal and B-phase signal) corresponding to a length or an angle is output from an encoder 1 to multipliers 2a and 2b. As these multipliers 2a and 2b, multiplying D / A converters are used. The multipliers 2a and 2b are supplied with outputs from ROMs 8a and 8b constituting the storage element 8, which will be described later, together with the clock signal CLK.

The analog A-phase signal from the encoder 1 is input to the reference voltage input terminal (ref) of the multiplier 2a, and the follow-up signal C from the ROM 8a is input to the multiplier 2a.
Is configured to be input digitally. Similarly, the multiplier 2b is configured such that the analog B-phase signal from the encoder 1 is input to the reference voltage input terminal (ref), and the follow-up signal D from the ROM 8b is input digitally. .

The outputs of the multipliers 2a and 2b are output to an adder / subtracter (here, a subtractor) 3. Then, the operation result E of the adder / subtractor 3 is inputted to the comparators 4a and 4b and compared with the reference voltages + Vref 5a and -Vref 5b.

Here, the output F of the comparator 4a operates so as to become LOW when the signal E of the operation result exceeds + Vref, and to return to HIGH when the signal E falls below + Vref. The output G of the comparator 4b operates so as to be LOW when the signal E is lower than -Vref, and to return HIGH when the signal E is higher than -Vref.

The output signals F and G of the comparators 4a and 4b are input to an up / down (UP / DOWN) counter 7 via AND gates 6a and 6b, respectively. The signal F is gated by the clock signal CLK by the AND gate 6a and becomes an up pulse of the up / down counter 7. The signal G is
Similarly, it is input to the counter 7 as a down pulse.

The count value φ which is the output of the counter 7
Is the address of the storage element 8 constituted by the ROMs 8a and 8b, and the follow-up signal is read out according to the table in the storage element 8.

In the encoder interpolating device thus constructed, the A-phase signal and the B-phase signal are converted from the encoder 1 as sine wave signals corresponding to the length or the angle by the multiplier 2a.
And 2b are supplied to the reference voltage input terminal ref. Then, the multiplier 2a multiplies the analog A-phase signal input to the reference voltage input terminal ref by the digital following signal from the ROM 8a in the storage element 8. Similarly, the multiplier 2b multiplies the analog B-phase signal input to the reference voltage input terminal ref by a digital following signal from the ROM 8b in the storage element 8. Here, the multipliers 2a and 2
In b, analog-to-digital conversion is performed in synchronization with the clock CLK.

The outputs of the multipliers 2a and 2b are
, And an output E is obtained. The subtraction result E is compared with the reference voltage Vref in the comparators 4a and 4b. As described above, the outputs F and G of the comparators 4a and 4b output a low level (LOW) or a high level (H) according to the comparison result with the reference voltages 5a and 5b, respectively.
IGH) is obtained.

The comparators 4a and 4b
The outputs F and G are gated by a clock CLK at AND gates 6a and 6b, and input to an up / down counter 7 as an up pulse and a down pulse, respectively. Therefore, this up / down counter 7
Then, the signal E which is the output of the subtractor 3 is output from the comparator 4
The count value φ changes each time the voltage exceeds the reference voltage ± Vref in a and 4b.

This count value φ is equal to the value of RO in storage element 8.
The addresses become M8a and 8b, and the follow-up signal is read out according to the table in the storage element 8. In the above configuration, the A-phase signal and the B-phase signal are signals that are 90 degrees out of phase, and can be described as follows. A phase signal = R · sin θ B phase signal = R · cos θ Here, R represents the amplitude of the sine wave signal, and θ represents the phase that changes in proportion to the length or angle.

On the other hand, a table for reading cos φ using the phase φ as an address is stored in the ROM 8 a in the storage element 8, and the ROM 8 b is stored in the ROM 8 b using the phase φ as the address.
A table for reading nφ is stored.

Therefore, the follow-up signal C and the follow-up signal D are expressed as the count value φ of the up / down counter 7 as follows. Following signal C = cos φ Following signal D = sin φ Therefore, the outputs of multipliers 2a and 2b are R
Sin θ · cos φ and R · cos θ · sin φ, and the output E of the subtractor 3 is as follows: signal E = R · sin θ · cos φ−R · cos θ · sin φ = R · sin (θ−φ) That is, if the phase θ and the phase φ are equal, the signal E
Turns out to be zero.

The reference voltage Vref of the comparator 4a is
Is set as Vref = R · sinγ, the comparator 4a determines that θ−φ> γ
Becomes HIGH when. That is, the actual phase θ
Has changed to the plus (+) side by more than γ with respect to the following phase φ. Conversely, the comparator 4b calculates θ−
It becomes HIGH when φ <(− γ). That is,
It is detected that the actual phase θ has changed to the minus (−) side by more than (−γ) with respect to the following phase φ.

When these detection results are input to the up / down counter 7, the phase φ changes following the phase θ, and in the next clock, cos with the new φ as the address is used.
φ and sinφ are read from the ROMs 8a and 8b.

That is, the interpolation device according to the present invention comprises a subtractor 3
Is locked so that the output E is always substantially zero. The deviation from the phase lock is input as an up pulse and a down pulse to a counter, a servo circuit, and the like (not shown).

FIG. 2 shows a ROM 8 using the phase φ as an address.
It is a schematic diagram of the storage content in a. In this case, ROM is 4
If a bit address is used, a phase angle of 360
The rotation is divided into 16 sections (identified by numbers 0 to 15 in FIG. 2). And, for example, output 8
Bits, the value da of the interpolation data for address n
ta is determined by data = cos ((360/16) · n) · 127.

The contents stored in the ROM 8b can be obtained in the same manner. Thus, RO
Since it is possible to adopt a configuration in which the addresses of M8a and 8b are used as phases and the sine and cosine are used as interpolation data, there is room in the address space even if the division is high. Further, since the phase shift is detected in the form of sin (θ−φ) and is controlled so as to become zero, the influence of the change in the amplitude of the A-phase signal and the B-phase signal is reduced. For example, when the amplitude is halved,
When X is almost 0, since sinX is almost X,
The phase resolution is only doubled and is not accumulated in the measured value.

Further, the up pulse and the down pulse are basically output in real time in synchronization with the clock with respect to the change of the phase θ. Does not occur,
Although not shown, the influence of noise is not transmitted to the length measurement counter, the servo circuit, and the like at the subsequent stage, so that only the necessary band can be transmitted without delay.

The above effects can be realized without specially changing the circuit scale as compared with the conventional encoder interpolation device. Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the encoder interpolation device of the present invention. In the embodiment described below, the same parts as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The second embodiment has a configuration in which a change in the amplitude of a sine wave signal is further considered in comparison with the first embodiment. In FIG. 3, an arithmetic unit 10 for calculating an amplitude is constituted by multipliers 11a and 11b of a multiplication type D / A converter and an adder 12 here.

That is, the A-phase signal (Rsinθ) from the encoder 1 is input to the reference voltage input terminal ref of the multiplier 11a, and is multiplied by the output sinφ of the ROM 8b. The B-phase signal (Rcos θ) from the encoder 1 is input to the reference pressure input terminal ref of the multiplier 11b,
a is multiplied by the output cos φ.

The results of these two multiplications are added by the adder 12. Then, the result of this addition is R · cos θ · cos φ + R · sin θ · sin φ = R
cos (θ−φ). As described above, since (θ−φ) is almost 0, the value of Rcos (θ−φ) is almost R. Therefore, the output of the adder 12, that is, the output of the arithmetic unit 10, is
It can be equal to the amplitude R.

The output R of the arithmetic unit 10 is supplied to the comparator 4a.
And 4b are supplied to the level setting unit 13 which determines the reference voltages. By inputting the addition result R of the adder 12 in the arithmetic unit 10 to the level setting unit 13, the reference voltage Vref changes in proportion to the amplitude R.

The level setting section 13 includes a voltage dividing resistor R11,
R12, voltage dividing resistors R21 and R22, and an inverter 14. Then, for example, the reference voltage Vref is obtained as follows. Vref = (R11 / (R11 + R12)). R In this way, the phase resolution can always be kept high regardless of the amplitude of the sine wave signal.

FIG. 4 is a block diagram showing a third embodiment of the encoder interpolation device according to the present invention. In FIG. 4, the A-phase signal and the B-phase signal output from the encoder 1 are supplied to multipliers 2a and 2b via gain control amplifiers 16a and 16b. The arithmetic unit 10
Is supplied to the divider 21 in the gain setting unit 20. The divider 21 performs an operation so that the output (amplitude) R has a predetermined amplitude r. This divider 2
1 is output from the gain control amplifier 16a
And 16b.

As described above, in the third embodiment, the A-phase signal and the B-phase signal are set so that the amplitude R obtained in the same manner as in the second embodiment becomes a predetermined amplitude r. Can be gain controlled. In this case, r / R is calculated by the gain setting unit 20, and the calculated value is used as the gain control amplifiers 16a and 16a.
By setting the gain to b, the amplitude of the sine wave input to the multipliers 2a and 2b is kept constant.

Thus, the same effects as in the above-described second embodiment can be obtained. According to the above embodiment of the present invention, the following configuration can be obtained.
That is, (1) an encoder that outputs signals that can be converted into distances that differ in phase by 90 degrees from each other according to the length or angle, and a first that multiplies a tracking signal to be generated by a signal that can be converted into the distance. And a second multiplier, an adder / subtractor for adding / subtracting the outputs of the first and second multipliers, and comparing the output of the adder / subtractor with predetermined first and second thresholds, and according to the comparison result, Output the first and second state signals
And a second comparator, and a counter that counts the first and second state signals output from the first and second comparators as up / down pulses.
A storage element storing the tracking signal corresponding to the count value of the counter.

(2) In the encoder interpolating apparatus according to the above (1), the storage element stores an address corresponding to an address divided into predetermined sections having a phase angle of 360 ° based on the count value of the counter. An encoder interpolation device for storing sine and cosine data.

(3) In the encoder interpolation apparatus according to the above (2), an arithmetic unit for calculating the amplitude of the signal which can be converted to the distance, and the level of the threshold value of the comparator according to the amplitude. And a level setting unit for changing the level.

(4) In the encoder interpolating apparatus according to the above (2), an arithmetic unit for calculating the amplitude of the signal that can be converted to the distance, and a gain for controlling the gain of the signal that can be converted to the distance An encoder interpolation device, further comprising: a control amplifier; and gain setting means for determining a gain of the gain control amplifier according to the amplitude. (5) The encoder interpolation device according to (3) or (4), wherein the signal that can be converted into the distance is a sine wave signal.

[0047]

As described above, according to the present invention, it is possible to provide an encoder interpolating device that can relatively easily increase the number of divisions without deteriorating the real-time property and without changing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an encoder interpolation device according to the present invention.

FIG. 2 is a schematic diagram of contents stored in a ROM 8a using a phase φ as an address.

FIG. 3 is a configuration diagram showing a second embodiment of the encoder interpolation device of the present invention.

FIG. 4 is a configuration diagram showing a third embodiment of the encoder interpolation device of the present invention.

FIG. 5 illustrates a conventional encoder interpolation device.
It is a schematic diagram of a storage device having 256 storage cells.

[Explanation of symbols]

 Reference Signs List 1 encoder, 2a, 2b, 11a, 11b multiplier, 3 adder / subtractor (subtractor), 4a, 4b comparator, 6a, 6b AND gate, 7 up (UP) / down (DOWN) counter, 8 storage element, 8a, 8b ROM, 10 arithmetic units, 12 adders, 13 level setting units, 14 inverters, 16a, 16b gain control amplifiers, 20 gain setting units, 21 division units.

Claims (3)

[Claims] 1. The method according to claim 1, further comprising the steps of:
An encoder that outputs a signal that can be converted to a distance having a different phase, a first and a second multiplier that multiplies a follow-up signal to be generated and a signal that can be converted to the distance, and the first and the second An adder / subtracter for adding / subtracting the output of the multiplier; and first and second comparators for comparing the output of the adder / subtracter with predetermined first and second threshold values and outputting first and second state signals according to the comparison result. A second comparator, a counter that counts the first and second state signals output from the first and second comparators as an up pulse / down pulse, and the following signal corresponding to the count value of the counter is: A storage element for storing the sine and cosine data for the address, which is divided into predetermined sections with a phase angle of 360 ° rotation based on the count value of the counter. The encoder interpolation apparatus, characterized by. 2. The encoder interpolation device according to claim 1, wherein a calculator for calculating an amplitude of the signal convertible to the distance, and a level of a threshold value of the comparator is changed according to the amplitude. An encoder interpolation device, further comprising: level setting means. 3. The encoder interpolation device according to claim 1, wherein an arithmetic unit that calculates an amplitude of the signal that can be converted to the distance, and a gain control amplifier that controls a gain of the signal that can be converted to the distance. And a gain setting means for determining a gain of the gain control amplifier according to the amplitude.