JPH1141100A - Digital-to-analog converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of noise due to switching noise generated at the time of output variation of each DA converting circuit(DAC) by operating only a necessary number of DACs and fixing the outputs of other DACs in consideration of a small variation quantity of output data when a small signal is continuously inputted. SOLUTION: When either the level of one of an input signal, or the output signal of a digital filter, or the output signal of a noise shaper is below a set level for longer than a certain period, only part of a 1-bit D/A converter array is placed in operation. A level detector 18 detects the output level of the noise shaper 12 and controls a decoder 13. For example, when the noise shaper 12 continues to output a small signal of <=±1, the output values of the 1-bit D/A converter array 14 are fixed to 1 or 0 except 3 to 4 converters and the decoder 13 outputs such data that data are circulated by the remaining DACs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter for converting a digital signal into an analog signal.

[0002]

2. Description of the Related Art Conventionally, a digital-to-analog converter for converting an input digital signal into an analog signal has been widely used in digital equipment for processing digital signals.

As this digital / analog converter, there is an oversampling type digital / analog converter which performs digital / analog conversion at a sampling frequency higher than the sampling frequency of the digital input signal. Are known.

FIG. 2 is a block diagram showing the configuration of a conventional digital-to-analog converter. In FIG.
Is a digital input terminal, 21 is a digital filter (hereinafter, referred to as DF), 22 is a noise shaper (hereinafter, NS)
, 23 is a decoder (hereinafter referred to as DEC), 2
4 is a 1-bit digital-analog converter train (hereinafter, D
AC), 25 is an analog adder (Σ), 26 is a digital / analog conversion circuit, and 27 is an analog output terminal.

The digital input terminal 20 is controlled by the DF 21.
After the sampling frequency fs of the digital signal input from the DF 21 is multiplied by n (n ≧ 2 and 64 in this case), the digital signal output from the DF 21 The length is limited and the frequency characteristic of the noise is changed to a predetermined characteristic.
Here, it is assumed that an NS (noise shaper) having a tertiary characteristic is used, and the output Y with respect to the input X is represented by (Equation 1).

[0006]

(Equation 1)

The DEC 23 outputs m 1-bit signals corresponding to the digital signals output from the NS 22, and these signals are output to the DAC 24.
The DAC 24 includes all uniform m 1-bit digital / analog converters from the first 1-bit digital / analog converter (DAC-1) 241 to the m-th 1-bit digital / analog converter (DAC-m) 244. After being added by an analog adder 25, the analog signals output from the m analog signals, which are constituted by analog converters, are output from an analog output terminal 27 as analog signals of this device. Further, the digital / analog conversion circuit 26 includes a DAC 24
And an analog adder 25.

[0008] The digital-to-analog converter of FIG.
The digital input signal is converted into a digital signal having a sampling frequency of 64 fs and 11 gradations (referred to as 11p) by the DF 21 and the NS 22, and then converted into m 1-bit signals by the DEC 23.
This is a so-called oversampling type digital-to-analog converter which converts a digital signal into an analog signal at a higher sampling frequency.

FIG. 3 shows an example of the configuration of the DEC 23 shown in FIG. In FIG. 3, reference numeral 30 denotes a pointer which outputs the remainder of the accumulated value of the input signal. Reference numeral 31 denotes a ROM (read-only memory) which outputs m-bit data corresponding to an address where the input signal is at the lower level and the output of the pointer 30 is at the upper level. Here m = 10
(= P-1).

The operation of the DEC 23 shown in FIG. 3 will be described below. First, the pointer 30 accumulates the 11-level signals (0 to 10) output from the NS 22 in FIG. Therefore, the output is 0-9
It becomes street.

Next, an address having the input signal as the lower order and the output signal of the pointer 30 as the upper order is inputted to the ROM 31,
Obtain 10-bit data. The 10-bit data represents ten 1-bit signals. The relationship between the address (decimal number) and the data (binary number) at this time is shown in (Table 1).

[0012]

[Table 1]

Referring to Table 1, 10-bit data is "1" as indicated by the lower address of the address, that is, the value of the input signal, and the sum of each bit is equal to the input signal. Also, the upper address, that is, the pointer 30
Are shifted to the left by the value of the output signal, and the overflowing digits are circulated so as to appear from the right.

By defining the ROM 31 as shown in (Table 1), data is output as shown in (Table 2), for example.

[0015]

[Table 2]

As can be seen from (Table 2), the number of "1" indicated by the numerical value of the input signal is output so as to circulate through the 10-bit data.
This indicates that there is no correlation with a specific bit of the 0-bit data. For this reason, even if there is a variation between the outputs of the DAC 24 to which the 10-bit data is connected, it is possible to reduce the occurrence of distortion and noise in the signal band.

[0017]

However, in the above-mentioned conventional digital-to-analog converter, since all DAC-1 to DAC-m always operate, the output data of each DAC changes. The analog noise level generated at the time of inputting is almost the same even when a small signal is input. Therefore, noise is particularly noticeable when a small signal is input,
There was a problem that it was disadvantageous in practical use.

The present invention solves the above-mentioned conventional problems, and suppresses the generation of noise due to switching noise generated when the output of each DAC changes, thereby improving the S / N ratio when a small signal is input. To provide a digital-to-analog conversion device that can

[0019]

In order to solve the above-mentioned problems, the digital-to-analog converter of the present invention takes into consideration that the amount of change in output data is small when small signal input continues. Only the required number of DACs are operated, and the output of other DACs is fixed.

As described above, the generation of noise due to switching noise generated when the output of each DAC changes can be suppressed, and the S / N ratio when a small signal is input can be improved.

[0021]

DETAILED DESCRIPTION OF THE INVENTION A digital-to-analog converter according to a first aspect of the present invention is a digital filter for increasing the sampling frequency of an input digital signal by a factor of k (k.gtoreq.2); A noise shaper that changes a frequency characteristic of noise to predetermined characteristics together with word length restriction, a decoder that receives an output of the noise shaper as input, and converts the output to a 1-bit signal sequence corresponding to the input value; Level detecting means for detecting a level of a signal, an output signal of the digital filter or an output signal of the noise shaper, and controlling an output operation of the decoder; and a 1-bit D for converting an output of the decoder into an analog signal. / A converter train;
An analog adder for adding each analog output of the 1-bit D / A converter sequence, wherein the decoder cyclically outputs a number of 1-bit signals corresponding to the output value of the noise shaper. And the level detecting means is
When detecting that the level of either the input signal, the output signal of the digital filter, or the output signal of the noise shaper is lower than a set level for a predetermined period or more, the 1-bit D / A converter row Is configured to control the decoder so that only a part of the decoder operates.

According to this configuration, when small signal input continues, taking into account that the amount of change in output data is small,
Only the required number of DACs are operated, and the output of other DACs is fixed.

Hereinafter, a digital-to-analog converter according to an embodiment of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the digital-to-analog converter of the present embodiment. In FIG. 1, 10 is a digital input terminal, 11 is a digital filter, 12 is a noise shaper, 13 is a decoder,
4 is a 1-bit D / A converter sequence (abbreviation for 1-bit digital-analog converter sequence), 15 is an analog adder (Σ), 16 is a D / A conversion circuit (abbreviation for digital-analog conversion circuit), 17 Is an analog output terminal, and 18 is a level detector as level detecting means.

Except for the decoder 13, the digital input terminal 10 to the analog input terminal 17 are the same as the digital input terminal 20 to the analog input terminal 27 in FIG. 2 and have the same function here. Is omitted.

The level detector 18 is a part of the noise shaper 12
, And controls the decoder 13. For example, as shown in (Table 3), when a small signal continues to output only the output (-1, 0, +1) within ± 1 of the noise shaper 12, the 1-bit D / A converter train 14 3
The output value is fixed to 1 or 0 except for 4 (here, 4), and control is performed so that the decoder 13 outputs data that circulates the data with the remaining DAC.

The shaded portions in Table 3 represent bits fixing data. Here, in order to make the input signal of the decoder 13 equal to the number of output '1's, the output signal of the noise shaper 12 is given an offset of +5.

[0027]

[Table 3]

As described above, when small signal input continues, taking into account that the amount of change in output data is small,
Only the required number of DACs are operated, and the output of other DACs is fixed.

As a result, it is possible to suppress the generation of noise due to switching noise generated when the output of each DAC changes, and to improve the S / N ratio when a small signal is input.
In the above description of the embodiment, the level detector 18
Has been described as an example in which a signal whose level is to be detected is output from the noise shaper 12, but a configuration in which the level of an input signal from the digital input terminal 10 or an output signal of the digital filter 11 is detected can be similarly implemented. The same effect can be obtained.

[0030]

As described above, according to the present invention, when a small signal continues to be input, only the required number of DACs are operated in consideration of the small amount of change in the output data, and the other DACs are operated. For DACs, their outputs are fixed.

Therefore, it is possible to suppress the generation of noise due to switching noise generated when the output of each DAC changes, and to improve the S / N ratio when a small signal is input.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital-to-analog converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional digital-to-analog converter.

FIG. 3 is a block diagram showing an example of a decoder in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Digital input terminal 11 Digital filter 12 Noise shaper 13 Decoder 14 1-bit D / A converter train 15 Analog adder 16 D / A conversion circuit 17 Analog output terminal 18 Level detector

Claims (1)

[Claims] 1. A digital filter for increasing a sampling frequency of an input digital signal by a factor of k (k.gtoreq.2), receiving an output of the digital filter as input, changing a word length limit and changing a noise frequency characteristic to a predetermined characteristic. A noise shaper to be input, a decoder which receives an output of the noise shaper as an input, and converts the output to a 1-bit signal sequence corresponding to the value of the input, and outputs an input signal, an output signal of the digital filter, or an output signal of the noise shaper. Level detecting means for detecting an output level of the decoder, controlling the output operation of the decoder, a 1-bit D / A converter train for converting the output of the decoder into an analog signal, and a 1-bit D / A converter train. And an analog adder for adding an analog output, wherein the decoder is configured to control the decoder according to a value of an output of the noise shaper. And outputs the number of 1-bit signals cyclically, and the level detection means sets the level of any of the input signal, the output signal of the digital filter, or the output signal of the noise shaper for a predetermined period or more. A digital-to-analog converter configured to control the decoder so that only a part of the 1-bit D / A converter array operates when detecting that the level is equal to or lower than the set level.