JPH1139170A - Input signal processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To selectively process input signals inputted at a period with a prescribed range independent of the timing of an input signal. SOLUTION: Counters 11 to 14 count the pulse numbers of a control signal only when respectively inputted enable signals ENA1 to ENA4 are active. The signals ENA1 to ENA4 are provided with an active interval of 1 ms successively deviated by 1 ms with a period of 4 ms. An adder 20 adds the counted output values of the counters 11 to 14 to give to a compactor 30, which compares the addition result with a reference value to determine and gives the result to a prohibiting gate 40 from an output terminal OUT. When the total value output of the adder 20 is not smaller than '4', a control signal prohibiting signal is given to the gate 40. The gate 40 controls the supply of an input control signal to the counters 11 to 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal processing system for selectively processing an input signal input at a predetermined period, and more particularly to an answerback processing of a control signal in a tracking radar transponder. The present invention relates to an input signal processing system suitable for processing control signals having a predetermined number of repetitions or less.

[0002]

2. Description of the Related Art Tracking radar transponders (RTs)
For example, it is a device mounted on a rocket and used for tracking the rocket and measuring the distance between the rocket and a ground station. The tracking radar transponder is generally configured as a small transceiver using a magnetron as a transmission tube, and transmits an answerback signal composed of a 5 GHz band pulse to a ground station when receiving a 5 GHz band pulse-like control signal. I do.

[0003] Such a tracking radar transponder is required to have the following functions, for example. That is,
When a control signal composed of a pulse signal is received, 1000
An answerback signal is output for a control signal of pps ("pps" indicates "Pulse Per Second", that is, a pulse repetition frequency, and 1000 pps indicates 1000 pulses per second), and a control signal exceeding 1000 pps is output. No answerback signal is output. The tracking radar transponder receives various pulses including a control signal requiring an answer back, and it is necessary to discriminate a required control signal from the received pulses and perform an answer back.

Japanese Patent Application Laid-Open No. 1-290041 discloses a CPU in an interrupt control circuit of a computer that performs information processing.
A technique relating to interrupt control for notifying a (central processing unit) of occurrence of a failure is disclosed.

That is, the interrupt control circuit disclosed in Japanese Patent Application Laid-Open No. 1-290041 includes a CPU, a fault detection circuit, a counter circuit, and a gate. CPU
Executes failure processing by interruption. The fault detection circuit generates a fault processing request and gives the request to the CPU. The gate temporarily inhibits the interrupt request signal. The counter circuit controls inhibition of the interrupt request signal by the gate for a predetermined time. The CPU can monitor the disabled state of the interrupt request signal via the data bus.

The interrupt control circuit disclosed in Japanese Unexamined Patent Publication No. 1-200411 has such a configuration, and when a request for fault processing is continuously generated in a short time, the counter circuit outputs the input interrupt request signal. The gate is given a signal over a period of time that determines the period of inhibition. The gate inhibits the interrupt request signal to the CPU during a period when the interrupt request signal inhibition signal is being input.

In this way, continuous execution of interrupt processing in the CPU can be suppressed, and pressure on other processing due to the CPU executing the failure interrupt processing many times in a short time can be avoided. .

[0008]

Problems to be Solved by the Invention
Although the configuration of the interrupt control circuit described in Japanese Patent Publication No. 1 is simple, it has the following problems.

The tracking radar transponder is, for example, 10
Processing a control signal of 00 pps or less is required as a function. In order to satisfy such a demand, if the unit time is, for example, 4 ms, it is necessary to process four (4 pulses) control signals per unit time.

When an input control signal is processed by using an interrupt control circuit disclosed in Japanese Patent Application Laid-Open No. 1-290041, control signal input is inhibited when four control signals are input within a unit time of 4 ms. It will be.

For example, as shown in FIG. 4, when four control signals are input within 4 ms, control signal input after the fourth control signal input is prohibited, and the control signals are processed during the prohibition period. do not do. Therefore, the control signal cannot be discriminated from the control signal during the prohibition period. Assuming that the prohibition period is a unit time, that is, 4 ms, in the worst case,
There is a possibility that a period of 4 ms may occur in which even one control signal cannot be processed, and the function condition required for the tracking radar transponder cannot be satisfied.

It is conceivable to set the prohibition period to 4 ms or less. In this case, however, the control signal is simply thinned out, and the condition required for the tracking radar transponder cannot be satisfied.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and can selectively process an input signal input in a predetermined range of cycle regardless of the timing of the input signal. An object of the present invention is to provide an input signal processing system applicable to answerback processing of a control signal.

[0014]

To achieve the above object, an input signal processing system according to the present invention is activated in a predetermined period and an active period of a predetermined period obtained by dividing the predetermined period into a plurality of periods. A plurality of counter means for counting input signals during an active period; an adding means for adding count values of the plurality of counter means; and a specification corresponding to a reference value of a processing condition of the input signal. Means for comparing with a value;
Input inhibiting means for inhibiting input of the input signal to the plurality of counter means based on a comparison result by the comparing means.

The plurality of counter means may have active periods equal to each other by equally dividing the predetermined period into a plurality.

The plurality of counter means may include means for resetting a count value at a start point of an active period.

[0017] The input prohibiting means may include means for prohibiting input of the input signal to the plurality of counter means when the added value exceeds the specified value.

The input prohibiting means may include prohibiting gate means for receiving the input signal, not passing the input to be prohibited, but passing other input signals and supplying the input signal to the plurality of counter means. Good.

The signal processing apparatus may further include signal processing means for executing a predetermined process in response to only the input signal which is not prohibited by the input prohibiting means.

In the input signal processing system according to the present invention, a plurality of counter means are activated in each of a predetermined period and an active period of a predetermined period obtained by dividing the predetermined period into a plurality, and the input signals in the active period are counted. The count values of the plurality of counters are added by adding means, and the added value of the adding means is compared by a comparing means with a specified value corresponding to a reference value of a processing condition of the input signal, and in response to the comparison result. The input prohibiting means prohibits the input of the input signal to the plurality of counter means. Therefore, the total count value of all the counter means which are sequentially and repeatedly activated is constantly monitored, and the input signal to the counter means is controlled based on the comparison with the specified value of the count value. It is possible to selectively process an input signal input in a period of a range.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the input signal processing system according to the present invention will be described with reference to FIGS.

FIG. 1 shows a configuration of an input signal processing system according to a first embodiment of the present invention. In this case, the input signal processing system is configured to perform processing for a control signal input of 1000 pps or less so that it can be used for a tracking radar transponder or the like.

The input signal processing system shown in FIG.
, A second counter 12, a third counter 13, a fourth counter 14, an adder 20, a comparator 30, and a prohibition gate 40. In this case, the unit time of the input processing is 4 ms, and the input control signal is 10 ms.
When the input control signal exceeds 00 pps, the input control signal is ignored, and a predetermined process is performed only when the input control signal is 1000 pps or less.

Each of the first to fourth counters 11 to 14 has an enable terminal ENA, a clock terminal CLK, and an output terminal OUT, respectively, and makes the clock terminal CLK active only when it is activated by the input of the enable terminal ENA. The applied input pulses are counted, and the count value is output to the output terminal OUT. These first to fourth
Enable signals ENA1, ENA for activating these first to fourth counters 11 to 14 at a predetermined timing.
A2, ENA3 and ENA4 are input to respective enable terminals ENA. The clock terminal CLK of each of the first to fourth counters 11 to 14 has an inhibit gate 4
A pulse-like control signal is commonly input via 0.

Therefore, the first to fourth counters 11 to 11
14 are input enable signals ENA1 to ENA1, respectively.
Only when ENA4 is in the active state, the number of pulses of the control signal is counted. In this case, the first to fourth counters 11 to 14 output enable signals ENA1 to ENA.
By 4, the count value is cleared each time the state is switched from the inactive (inactive) state to the active state.

The enable signals ENA1 to ENA4 supplied to the first to fourth counters 11 to 14 divide the unit time of 4 ms into four equal parts and set the active period of 1 ms to the first time.
To the fourth counters 11 to 14. That is, the enable signals ENA1 to ENA4 are
It has an active period of 1 ms, which is sequentially shifted by 1 ms at a period of 4 ms (see FIG. 2).

The adder 20 has input terminals IN1 to IN4 and an output terminal OUT, and the output count values from the output terminals OUT of the first to fourth counters 11 to 14 are input to the input terminals IN1 to IN4. The addition result is output from the output terminal OUT and provided to the comparator 30. That is, the adder 20 adds up all the output count values of the first to fourth counters 11 to 14 and constantly outputs the addition result to the comparator 30.
To supply.

The comparator 30 has an input terminal IN and an output terminal OUT, compares the addition result given from the adder 20 to the input terminal IN with a specified value, determines the result, and inhibits the determination result from the output terminal OUT. Give to gate 40. In this case, the prescribed value in the comparator 30 is set to “4” and the comparator 3
0 indicates that the control signal prohibition signal given to the prohibition gate 40 is “L” when the total value output of the adder 20 is “4” or more.
(Low level) ", and when the total value output is less than" 4 ", that is, equal to or less than" 3 ", the control signal inhibition signal given to the inhibition gate 40 is set to" H (high level) ". The control signal prohibition signal is "L" active. That is,
When the addition result becomes “4” or more, the comparator 30
A control signal prohibition signal is output from the output terminal OUT and supplied to the prohibition gate 40 to prohibit the input control signal from being input to the first to fourth counters 11 to 14.

The prohibition gate 40 applies an input control signal to the first to
The signal is supplied to the fourth counters 11 to 14 and the comparator 30
In response to the control signal prohibition signal from the control unit, the supply of the input control signal to the first to fourth counters 11 to 14 is controlled. That is, when the control signal prohibition signal provided from the comparator 30 is “H”, the prohibition gate 40 enters an input state, that is, a state in which an input control signal is input to the first to fourth counters 11 to 14. When the prohibition signal is “L”, an input prohibition state is set, that is, a state where input of an input control signal to the first to fourth counters 11 to 14 is prohibited.

Next, the operation of the above-described input signal processing system will be described with reference to a timing chart shown in FIG.

FIG. 2 shows a control signal input waveform to the inhibition gate 40, an output waveform of the inhibition gate 40, and the enable signal E.
NA1 to ENA4 waveforms, first to fourth counters 11 to 1
4, the output value of the adder 20 and the control signal prohibition signal waveform are shown. The first to fourth counters 11 to 14 count (up-count) only when the input enable signals ENA1 to ENA4 are at “H”, respectively. As described above, the enable signals ENA1 to ENA4 are When the count changes from "L" to "H", the count value is cleared and the output count value becomes "0".

Initially, first to fourth counters 11 to 14
Count value and the addition result of the adder 20 are all “0”
And During the first 1 ms period, when the enable signal ENA1 becomes “H”, the first counter 11
Becomes active, and counts the control signals passing through the prohibition gate 40. In this period, for example, if a one-pulse control signal is input as shown in FIG.
Counter 11 outputs a count value output from “0” to “1”.
And the output value of the adder 20 is also “1”. Therefore, since the addition result of the adder 20 is less than “4”, the comparator 30 keeps the control signal prohibition signal at “H”, does not prohibit the control signal, and maintains the previous state. . When the active period of 1 ms expires and the enable signal ENA1 becomes “L”, the first counter 11
Is in an inactive state, i.e., a pause state, but the count value output "1" is held until it is cleared the next time the first counter 11 is activated.

In the next 1 ms period, when the enable signal ENA2 becomes "H", the second counter 12 becomes active, and counts the control signal passing through the inhibition gate 40. In this period, for example, if a two-pulse control signal is input as shown in the drawing, the second counter 12 counts it, and the count value output changes from “0” → “1” → “2”. This count value and the count value of the first counter 11 are added, and the output value of the adder 20 becomes “1” → “2” → “3”. Therefore, at this time, the addition result of the adder 20 is less than “4”, and the comparator 30 outputs the control signal inhibition signal
The signal is kept at "H", and the control signal is not inhibited, and the state as before is maintained. When the active period of 1 ms expires, the second counter 12 goes into a sleep state,
The count value output “2” is held until it is cleared the next time the second counter 12 is activated.

At the next 1 ms and at the next 1 ms, the third and fourth counters 13 and 14 output enable signals ENA3 and ENA, respectively, as described above.
The signals are sequentially activated by NA4, but there is no control signal input during these periods, so that the outputs of the adder 20 and the comparator 30 do not change.

As described above, one cycle of the unit time of 4 ms expires, and further enters the cycle of the unit time of 4 ms. In the first 1 ms period, the enable signal EN
When A1 becomes “H”, the first counter 11 clears the count value and becomes active, and the inhibition gate 40
The control signals passing through are counted. In this period, for example, assuming that the first two pulses of the three-pulse control signal are input as shown in FIG.
1 is counted sequentially, and the count value output is “0”
→ “1” → “2”. This count value and the previous count value “2” of the second counter 12 are added,
The output value of the adder 20 is “2” → “3” → “4”. Therefore, at this time, the addition result of the adder 20 becomes “4”, and the comparator 30 outputs the control signal inhibition signal
As “L”, the control signal is prohibited. Therefore, the inhibition gate 40 is closed, and the control signal of the third pulse in this period is
The signal is blocked by the prohibition gate 40 and is not input to the counter 11. When this 1 ms active period expires, the first
Of the counter 11 becomes inactive, but the count value output “2” is held until it is cleared the next time the first counter 11 is activated.

In the next 1 ms period, when the enable signal ENA2 becomes "H", the second counter 12
The count value is cleared and becomes active, and the control signal passing through the inhibition gate 40 is counted. At this time,
Since the output value of the second counter 12 is “0”, the output of the adder 20 is “2”, which is less than “4”.
The comparator 30 releases the prohibition of the control signal by setting the control signal prohibition signal to “H”. Therefore, the prohibition gate 40 opens, and the input of the control signal to the second counter 12 is restarted. In this period, for example, if a two-pulse control signal is input as shown in FIG.
Counts sequentially, and the count value output changes from “0” to
“1” → “2”. This count value and the last 1
Is added to the count value “2” of the counter 11, and the output value of the adder 20 becomes “2” → “3” → “4”.
Therefore, at this time, the addition result of the adder 20 is “4”.
Thus, the comparator 30 sets the control signal inhibition signal to “L” and inhibits the control signal. Therefore, the prohibition gate 40
Is closed, and the subsequent control signal is blocked by the inhibition gate 40 and is not input to the counter 11. When the 1 ms active period expires, the second counter 12 goes into a sleep state, but the count value output “2” is held until it is cleared the next time the second counter 12 is activated. You.

In the next 1 ms and the next 1 ms as well, the third and fourth counters 13 and 14 output enable signals ENA3 and ENA, respectively, as described above.
The active state is sequentially activated by NA4. During these periods, the first and second counters 11 and 12 are activated.
Does not change, and the output of the adder 20 maintains the state of "4". Therefore, all control signal inputs are prohibited by the prohibition gate 40, and the outputs of the adder 20 and the comparator 30 do not change.

Thus, the next one cycle of the unit time of 4 ms expires, and the cycle of the next unit time of 4 ms starts. In the first 1 ms period, the enable signal EN
When A1 becomes “H”, the first counter 11 clears the count value and becomes active, and the inhibition gate 40
The control signals passing through are counted. At this time, the output value of the first counter 11 becomes “0”,
Is "2" and less than "4", the comparator 30 sets the control signal prohibition signal to "H" and releases the prohibition of the control signal. Therefore, the prohibition gate 40 opens,
The input of the control signal to the first counter 11 is restarted.
In this period, for example, if two pulses are input as shown in the figure, the first counter 11 sequentially counts them, and the count value output changes from “0” → “1” → “2”. This count value and the previous count value “2” of the second counter 12 are added, and the output value of the adder 20 becomes “2” → “3” → “4”. Therefore, at this time, the addition result of the adder 20 becomes “4”, and the comparator 3
0 sets the control signal inhibition signal to "L" to inhibit the control signal. Therefore, the prohibition gate 40 is closed, and the control signal is not input to the counter 11. When the 1 ms active period expires, the first counter 11 goes into a sleep state, but the count value output “2” is held until it is cleared the next time the first counter 11 is activated. You.

In this manner, every 1 ms, the adder 20 determines whether the total number of control signal input pulses in the 1 ms period and the immediately preceding 3 ms period is 4 or more (corresponding to 1000 pps or more). Always judge from output,
As soon as the number of pulses becomes four or more, the comparator 30 outputs a control signal inhibition signal to inhibit the input of the control signal. The control signal input prohibition period is set such that every time a new 1 ms period elapses after the successive 1 ms period, the total number of control signal pulses that have passed through the prohibition gate 40 during the immediately preceding 3 ms period is 4 or more. For example, the prohibition state of the control signal is maintained, and if the total number of the control pulses is less than 4, the prohibition state of the control signal is released. That is, the control signal input is controlled by checking every 1 ms whether or not the number of pulses of the control signal during the 4 ms period immediately before is four or more.

Accordingly, the total count value of the first to fourth counters 11 to 14 which are sequentially and repeatedly activated is constantly monitored, and based on comparison of the count value with a specified value, the first to fourth counters 11 to 14 are counted. Since the input signals to are controlled, the input signals input at a repetition frequency of 1000 pps or less can be selectively processed regardless of the timing of the input signals.

In the above description, the unit time is 4 ms.
The control signals in the period obtained by dividing the unit time into four are respectively counted using the four counters 11 to 14, but the unit time and the number of counters can be appropriately set as desired. The range of the repetition frequency of the control signal to be discriminated can also be set according to the comparison reference value and the comparison condition in the comparator 30. Therefore, the range is not limited to 1000 pps or less, and at least one of the upper limit and the lower limit may be appropriately set as desired. Can be set.

When the input signal processing system having the above-described configuration is applied to a tracking radar transponder, a circuit for processing an input control signal may be controlled using a control signal inhibition signal. As shown, the present invention can be more easily applied to a tracking radar transponder.

FIG. 3 shows the configuration of an input signal processing system according to a second embodiment of the present invention. In this case, the input signal processing system is configured to generate an answerback signal for a control signal input of 1000 pps or less in order to be applied to a tracking radar transponder.

The input signal processing system shown in FIG.
, A second counter 12, a third counter 13, a fourth counter 14, an adder 20,
An answerback signal generator 50 is provided in addition to the comparator 30 and the inhibit gate 40. Also in this case, similarly to the case of FIG. 1, the unit time of the input processing is set to 4 ms. When the input control signal exceeds 1000 pps, the input control signal is ignored, and only when the input control signal is 1000 pps or less. Generate an answerback signal. In the following, first, the same components as those in FIG. 1 are the same as those in FIG. 1, and therefore the configuration thereof will be briefly described, and then the answerback signal generator 50 added in FIG. 3 will be described in detail.

The first to fourth counters 11 to 14 count input pulses supplied to the clock terminal CLK only when they are activated by the input of the enable terminal ENA, and output the count value to the output terminal OUT. Output. These first to fourth counters 11, 12, 13
And 14 include an enable signal E for activating these counters 11 to 14 at a predetermined timing.
NA1, ENA2, ENA3 and ENA4 are input to respective enable terminals ENA. First to first
The clock terminals CLK of the fourth counters 11 to 14 include:
A pulse-like control signal is commonly input via the inhibition gate 40.

That is, the first to fourth counters 11 to 1
4 are input enable signals ENA1 to ENA
Only when NA4 is in the active state, the number of pulses of the control signal is counted. In this case, the first to fourth counters 1
The count values of 1 to 14 are cleared each time they are switched from the inactive state to the active state by the enable signals ENA1 to ENA4. The enable signals ENA1 to ENA4 are sequentially set to 1 at a period of 4 ms.
This signal has an active period of 1 ms shifted by ms.

The adder 20 receives input count values from the output terminals OUT of the first to fourth counters 11 to 14 at input terminals IN1 to IN4, outputs the addition result from the output terminal OUT, and outputs Give to. Comparator 30 compares the result of addition provided from adder 20 to input terminal IN with a prescribed value to determine the result, and provides the result of determination to output gate OUT to inhibit gate 40. In this case, the comparator 30
The specified value is “4”, and the total value output of the adder 20 is “4”.
In the above case, the control signal prohibition signal given to the prohibition gate 40 is set to “L”, and when the total value output is less than “4”, that is, “3” or less, the control signal prohibition signal given to the prohibition gate 40 is set to “L”. H ”.

The inhibit gate 40 controls the supply of the input control signal to the first to fourth counters 11 to 14 according to the control signal inhibit signal from the comparator 30. That is, when the control signal prohibition signal provided from the comparator 30 is “H”, the prohibition gate 40 enters a state in which the input control signal is input to the first to fourth counters 11 to 14, and the control signal prohibition signal is “ When L ", the input is inhibited, that is, the input of the input control signal to the first to fourth counters 11 to 14 is inhibited.

The answerback signal generator 50 generates and outputs an answerback signal in response to the input control signal output from the inhibit gate 40. That is, the inhibition gate 40 allows only the control signal corresponding to the repetition frequency of 1000 pps or less to pass and blocks the control signal corresponding to the repetition frequency of 1000 pps or less. Only the control signal corresponding to the frequency is provided. Therefore, the answerback signal generation unit 50
An answerback signal is generated in response to only a control signal corresponding to a repetition frequency of ps or less.

In this way, for example, the answerback signal generator 50 can generate an answerback signal in response to only a control signal corresponding to a preset repetition frequency of 1000 pps or less. If used, a tracking radar transponder that can satisfy the functional conditions required for the tracking radar transponder can be configured.

[0052]

As described above, according to the present invention, the total count value of all the counter means which are sequentially and repeatedly activated is constantly monitored, and the input to the counter means is determined based on the comparison with the specified value of the count value. By controlling the signal, it is possible to selectively process the input signal that is input with a predetermined range of period regardless of the timing of the input signal, and it is also effectively applied to the answerback processing of the control signal in the tracking radar transponder An input signal processing system that can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an input signal processing system according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the system in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an input signal processing system according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining a problem in a conventional configuration.

[Explanation of symbols]

 11 to 14 First to fourth counters 20 Adder 30 Comparator 40 Prohibition gate 50 Answer back signal generator

Claims (6)

[Claims] 1. A plurality of counter means each being activated in a predetermined period and an active period of a predetermined period obtained by dividing the predetermined period into a plurality of periods, and counting input signals in the active period, and counting by the plurality of counter units. Adding means for adding a value; comparing means for comparing the added value of the adding means with a prescribed value corresponding to a reference value of a processing condition of the input signal; and the plurality of counters based on a comparison result by the comparing means. Input inhibiting means for inhibiting input of the input signal to the input means. 2. The input signal processing system according to claim 1, wherein said plurality of counters have active periods equal to each other by dividing said predetermined period into a plurality of equal parts. 3. The input signal processing system according to claim 1, wherein said plurality of counters include means for resetting a count value at a start point of an active period. 4. The apparatus according to claim 1, wherein said input prohibiting means includes means for prohibiting input of said input signal to said plurality of counter means when said added value exceeds said prescribed value. 4. The input signal processing system according to any one of 3. 5. The input prohibiting means includes prohibiting gate means for receiving the input signal, not passing the input signal to be prohibited, but passing other input signals and supplying the input signal to the plurality of counter means. The input signal processing system according to any one of claims 1 to 4, wherein: 6. The apparatus according to claim 1, further comprising a signal processing unit that executes a predetermined process in response to only the input signal that is not inhibited by the input inhibition unit. An input signal processing system as described.