JPH1131925A - High frequency mixer and integrated circuit for the mixer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively apply the frequency conversion to the high frequency signals and also to improve the mutual conversion distortion characteristics of the high frequency signals by specifying the characteristics of FET(field effect transistors) of both high and low voltage levels and also inputting a high frequency signal or a local signal to the gate terminal of every FET. SOLUTION: The FET 1 and 2 which are cascaded to each other are placed between the high and low voltage terminals of a power supply. The frequency of a high frequency signal is converted by a local signal, and an intermediate frequency signal is outputted via a drain terminal of the FET 2 of a high voltage level. The characteristics of both FET 1 and 2 are set, so that the absolute value of threshold voltage of the FET 2 exceeds at least the knee voltage of the FET 1 of a low voltage level. At the same time, a high frequency signal is inputted to the gate terminal of the FET 2 with a local signal inputted to the gate terminal of the FET 1 respectively. Therefore, the local signal of an amplitude that varies the working point in a wide range of voltage is inputted to change the drain-source current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-frequency mixer and a high-frequency mixer integrated circuit used for converting the frequency of a high-frequency signal in a mobile communication device, a microwave communication device, a satellite communication device, and the like. The present invention relates to a high-frequency mixer and a high-frequency mixer integrated circuit that receive a high-frequency signal and a local signal, convert the high-frequency signal with the local signal, generate an intermediate frequency signal, and output the intermediate-frequency signal.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a "1.0 V GaAs R receiver for front-end IC for mobile communication equipment (1.0 V GaAs R).
eceiver Front-end IC for Mobile Communication Equi
pment ")" (IEEE 1996 Microwave and Millimeter-Wave Monolithic Integrated Circuit Symposium)
Monolithic Circuits Symposium Proceeding), 7th
FIG. 7 is a circuit diagram showing a conventional high frequency mixer disclosed in (7).

In FIG. 1, reference numeral 40 denotes an input terminal of the high-frequency signal to the high-frequency mixer, 41 denotes an input terminal of the local signal to the high-frequency mixer, 42 denotes an output terminal of the intermediate frequency signal, and A high voltage terminal of a power source (not shown) is connected to the terminal 42. Reference numeral 102 denotes a high-voltage side field-effect transistor (hereinafter abbreviated as a high-voltage FET) having a drain terminal connected to the output terminal.
Is a low-voltage side field-effect transistor (hereinafter abbreviated as low-voltage FET) having a source terminal and a drain terminal connected to the high-voltage FET 102, and 9 is the low-voltage FET.
A self-biasing resistor 9 for connecting the source terminal 101 to a low-voltage terminal (ground plane) of the power supply;
Is a bypass capacitor disposed in parallel with the self-biasing resistor 9.

In the high-frequency mixer of the above document, the gate terminal of the high-voltage FET 102 is grounded to the ground plane via the high resistance 4 and the high-frequency signal terminal 40 is connected to the low-voltage FET 10.
One gate terminal is grounded via the high resistance 3 to the ground plane and connected to the local signal terminal 41.

Next, the operation will be described. First, the bias state of each field effect transistor will be described. The gate terminal of the high voltage side FET 102 and the low voltage side FET 10
The gate terminals 1 are grounded to 0 V via high resistances 3 and 4, respectively. Therefore, when neither the high-frequency signal nor the local signal is input, the low-voltage side FET 101 is in a state where both the gate terminal and the source terminal are grounded, and the high-voltage side FET 102 is in a state where the gate terminal is grounded. Further, since a voltage is applied to the drain terminal of the high-voltage side FET 102 from the power supply, a constant bias current (Ids) corresponding to the characteristics of the two FETs is applied between the drain and the source of the two FETs 101 and 102. = Ids1 = Ids2) flows.

Then, the high-frequency signal and the local signal are input from the input terminals 40 and 41 under such a bias state. Then, each FET 101, 1
Since the gate terminal 02 is grounded via the high resistances 3 and 4, respectively, the potential fluctuates in accordance with the input signals. When the gate voltage of each of the FETs 101 and 102 fluctuates, a channel corresponding thereto is formed between the source terminal and the drain terminal, whereby the magnitude of the bias current (Ids = Ids1 = Ids2) fluctuates.

[0007] The current flowing to the output terminal of the intermediate frequency signal is an alternating current including a component corresponding to the voltage fluctuation of the high-frequency signal and a component corresponding to the voltage fluctuation of the local signal. In the high-frequency mixer, for example, by inserting a predetermined resistor between the power supply and the output terminal, the alternating current can be output as an intermediate frequency signal having a predetermined voltage fluctuation.

[0008]

Since the conventional high frequency mixer is constructed as described above, there is a problem that the high frequency signal cannot be efficiently frequency-converted by the local signal.

Hereinafter, the high-frequency mixer described in the above document will be described in detail by way of example. In the high-frequency mixer, the characteristics of the low-voltage side FET 101 are such that the threshold voltage Vth1 is in a deep depression mode of −1.0 V and the knee voltage Vknee 1 is set to 0.25 V. The characteristics of the high-voltage side FET 102 are such that the threshold voltage Vth2 is a shallow enhancement mode of −0.15 V and the knee voltage Vknee
2 is set to 0.3V.

Therefore, the combination of the characteristics of the two field effect transistors in the high frequency mixer is as shown in FIG. In the figure, the horizontal axis is the low-voltage side FET 101
Is the inter-stage voltage VF between the drain terminal of the high-side FET 102 and the drain terminal, and the vertical axis is the current Ids flowing between the drain and the source. 103 (solid line) is a characteristic line when the above-mentioned inter-stage voltage VF (that is, the source-drain voltage Vds1) is increased while the gate-source voltage of the low-voltage side FET 101 is controlled to a constant voltage.
When the interstage voltage VF is increased, the drain-source current Ids is substantially linearly increased until a predetermined knee voltage.
Increase, and the characteristic becomes substantially constant drain-source current Ids above the knee voltage. Also, the drain-source current Ids changes according to the magnitude of the gate-source voltage Vgs1, and when the gate-source voltage Vgs1 is increased, the drain-source current Ids increases.
The source-to-source current Ids also tends to increase. 104 (dotted line) is a characteristic line in the bias state of the high-voltage side FET 102, and shows a characteristic that when the inter-stage voltage VF increases from 0 V, the drain-source current Ids sharply decreases from the saturation current Idss2. When the voltage VF reaches the threshold voltage Vth2, no current flows at all. Note that the characteristics shown in FIG. 6 are obtained when the power supply voltage is sufficiently higher than the threshold voltage Vth and the knee voltage Vknee of the two FETs 101 and 102.

Then, as is clear from the characteristic diagram,
In the conventional high frequency mixer, the threshold voltage Vt on the higher voltage side than the knee voltage Vknee1 of the low voltage side FET 101
The characteristics of the two FETs 101 and 102 are set so that h2 becomes small.
Operating point 105 in the bias state of the low pressure side F
The voltage is much lower than the knee voltage Vknee1 of the ET101. Therefore, in the conventional high frequency mixer,
When the local signal is input to the gate terminal of the low-voltage side FET 101, the movement range of the operating point due to the input is within the narrow range much lower than the knee voltage Vknee1 of the low-voltage side FET 101 as indicated by the arrow in FIG. Will be moved.

As a result, in the conventional high-frequency mixer, a local signal can be input only at an amplitude at which the inter-stage voltage VF is within the moving range of the operating point. On the other hand, the moving range of the operating point is lower than the knee voltage Vknee1 of the low-voltage side FET 101, and even if the operating point moves, the drain-source current Ids does not largely change. Therefore, in the conventional high-frequency mixer, a local signal having a small amplitude must be input, and the local signal efficiently drain-source current Ids.
Cannot be changed, so that a high-frequency signal cannot be efficiently frequency-converted by the local signal.

In order to improve the frequency conversion efficiency, the knee voltage Vknee1 of the low-voltage side FET 101 is increased.
However, it is generally difficult to make the knee voltage of the FET very small, and conversion is not efficiently performed. Further, the high-voltage side F to which a sufficient drain-source voltage Vds2 is applied
It is conceivable that a local signal is input to the ET 102 and a high-frequency signal is input to the low-voltage FET 101. In such a case, however, the intermodulation distortion ( Another problem that the (tertiary distortion) characteristic is deteriorated occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to efficiently convert a high-frequency signal with a local signal, and furthermore, intermodulation distortion (third-order distortion) for the high-frequency signal. It is an object to realize a high-frequency mixer having good characteristics.

[0015]

According to a first aspect of the present invention, there is provided a high-frequency mixer according to the first aspect of the present invention, wherein the absolute value of the threshold voltage of the high-voltage FET is at least equal to or higher than the knee voltage of the low-voltage FET. In addition to setting the characteristics, a high-frequency signal is input to the gate terminal of the high-voltage side FET, and a local signal is input to the gate terminal of the low-voltage side FET.

According to a second aspect of the present invention, in the high frequency mixer, a DC bias voltage greater than 0 V is applied by a bias circuit to the gate terminal of the FET on the high voltage side, and a high frequency signal is input to the high voltage side FET. The gate terminal of the field effect transistor on the side is grounded and receives a local signal.

According to a third aspect of the present invention, there is provided a high frequency mixer, comprising: a setting circuit for outputting a set value of an interstage voltage between a drain terminal of a low voltage side FET and a source terminal of a high voltage side FET; A DC bias voltage greater than 0 V is output to the gate terminal of the high-side FET so as to detect and compare with the set value of the inter-stage voltage and to eliminate the voltage difference between the detected value and the set value of the inter-stage voltage. And a bias circuit composed of an output adjustment circuit.

According to a fourth aspect of the present invention, there is provided a high-frequency mixer formed simultaneously with the high-voltage side FET in the same semiconductor process, and a setting FET having a source terminal and a gate terminal connected to a low-voltage terminal of a power supply; And a setting resistor connected between the high-voltage terminal and the drain terminal of the setting FET. The voltage at the connection point between the drain terminal of the setting FET and the setting resistor is set to the gate of the high-voltage FET. A bias circuit for outputting a DC bias voltage to a terminal is provided.

According to a fifth aspect of the present invention, there is provided a high-frequency mixer comprising: a gate terminal of a high-side FET;
A matching circuit having a high-pass filter characteristic is connected to the gate terminal of the ET, and a high-frequency signal and / or a local signal are input to a predetermined gate terminal via the high-pass filter.

In the high frequency mixer integrated circuit according to the present invention, the matching circuit is formed by using a matching inductor, and all or a part of the matching inductor is formed by a bonding wire and / or a lead. Is what it is.

According to a seventh aspect of the present invention, there is provided a high-frequency mixer in which a stabilizing circuit having a low-pass filter characteristic is provided at a drain terminal of a high-voltage side FET.

According to an eighth aspect of the present invention, in the high frequency mixer integrated circuit, the stabilizing circuit includes a stabilizing resistor having one end connected to the drain terminal of the high voltage side FET, and a low voltage of the other end of the stabilizing resistor and the power supply. A stabilizing capacitor connected between the stabilizing capacitor connected to the terminal or the ground brain, and a stabilizing inductor having one end connected to a connection point between the stabilizing resistor and the stabilizing capacitor and outputting an intermediate frequency signal from the other end. That is, all or a part of the stabilizing inductor is formed of a bonding wire and / or a lead.

According to a ninth aspect of the present invention, in the high frequency mixer integrated circuit, the local signal lead for inputting a local signal and the high frequency signal lead for inputting a high frequency signal are opposite to each other in the package. It is assigned to.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a high-frequency mixer according to Embodiment 1 of the present invention. In the figure, 4
0 is an input terminal of the high-frequency signal to the high-frequency mixer, 41 is an input terminal of the local signal to the high-frequency mixer, and 42 is an output terminal of the intermediate frequency signal. Reference numeral 2 denotes a high-voltage side FET having a drain terminal connected to the output terminal, 1 denotes a low-voltage side FET having a drain terminal connected to the source terminal of the high-voltage side FET2, and 9 denotes a source terminal of the low-voltage side FET1. A self-biasing resistor 9 is connected to the ground plane, and a bypass capacitor 10 is disposed in parallel with the self-biasing resistor 9 and bypasses a local signal, a high-frequency signal, and an intermediate frequency signal.

A high resistance 3 has one end connected to the gate terminal of the low-voltage side FET 1 and the other end grounded to a low-voltage terminal (ground plane) of a power supply, and 4 has one end connected to the high-voltage side FET 2. A high resistance connected to the gate terminal and having the other end grounded to the ground plane is provided between the local signal input terminal 41 and the gate terminal of the low-voltage side FET 1 and has a high-pass filter characteristic. Matching circuit for local signal (matching circuit)
Reference numeral 6 denotes a high-frequency signal matching circuit (matching circuit) provided between the high-frequency signal input terminal 40 and the gate terminal of the high-voltage side FET 2 and having a high-pass filter characteristic.
It is. On the other hand, 7 is an intermediate frequency signal matching circuit in an intermediate frequency band provided between the drain terminal of the high-voltage side FET 2 and the output terminal of the intermediate frequency signal,
Reference numeral 8 denotes a power supply device in which the voltage of the high voltage terminal of the power supply is applied to the drain terminal of the high voltage side FET 2 via the intermediate frequency signal matching circuit and the low voltage terminal is connected to the ground plane. Note that the high-frequency mixer operates only with the power of the power supply device 8.

In the first embodiment, in particular, the threshold voltage Vth2 of the high-side FET 2
The characteristics of these two FETs 1 and 2 were designed so as to be higher than the knee voltage Vknee1 of T1. Therefore, this characteristic is as shown in FIG. In the figure, 1
Reference numeral 07 denotes an IV characteristic of the high-voltage side FET2, and reference numeral 103 denotes an IV characteristic of the low-voltage side FET1. In the characteristic diagram of the drain-source current Ids generated when the gate-source voltage is changed and the source-drain voltage is changed, the knee voltage is a voltage line where the current linearly increases according to the voltage. Is extended, and a voltage change line which becomes a constant current regardless of the voltage is extended to obtain a voltage corresponding to the intersection thereof.

The gate terminal of the high-voltage side FET 2 and the gate terminal of the low-voltage side FET 1 are grounded to 0 V via the high resistances 3 and 4, respectively. Therefore, in a bias state in which neither the high-frequency signal nor the local signal is input, the low-voltage side FET 1 is in a state where both the gate terminal and the source terminal are grounded, and the high-voltage side FET 2 is in a state where the gate terminal is grounded. A constant bias current (Ids = Ids1 = Id) corresponding to the characteristics of the two FETs is applied to the drain-source Ids of the two FETs 1 and 2.
s2) flows. The operating point at this time is shown at 108 in FIG.

Next, the operation will be described. The high-frequency signal and the local signal are input from the input terminals 40 and 41 to the high-frequency mixer in such a bias state. Then, since the gate terminals of the FETs 1 and 2 are grounded via the high resistances 3 and 4, respectively, the potentials change according to the input signals. And each FET
When the gate voltage fluctuates, a channel corresponding to the fluctuating gate voltage is formed between the source terminal and the drain terminal, whereby the magnitude of the bias current Ids fluctuates.

Thus, the current flowing to the output terminal of the intermediate frequency signal is an alternating current including a component corresponding to the voltage fluctuation of the high frequency signal and a component corresponding to the voltage fluctuation of the local signal. The high-frequency mixer can output the alternating current as an intermediate frequency signal having a predetermined voltage fluctuation, for example, by inserting a predetermined resistor between the power supply and the output terminal. For example,
FIG. 2 shows the variation of the operating point when a local signal is input.
At 109.

As described above, according to the first embodiment, as is apparent from FIG. 2, the local signal input to the low-voltage side FET 1 is such that the inter-stage voltage VF is lower than the knee voltage Vknee 1 of the low-voltage side FET 1. Input can be made with a large amplitude that increases. In addition, the operating point at the time of the bias can be set to a voltage substantially equal to the knee voltage, and the drain-source current Ids fluctuates greatly following the fluctuation of the local signal. Therefore, in the first embodiment, a local signal having a large amplitude can be input.
In addition, since the drain-source current Ids can be efficiently changed by the local signal, a high-frequency signal can be efficiently frequency-converted by the local signal, and the conversion gain as a mixer is remarkably improved.

Further, since the high-frequency signal is input to the high-side FET 2, amplification and modulation can be performed by the FET to which a sufficient drain-source voltage is applied, so that the intermodulation distortion is excellent.

Embodiment 2 FIG. FIG. 3 is a circuit diagram showing a configuration of a high-frequency mixer according to Embodiment 2 of the present invention. In the figure, reference numeral 14 denotes a bias circuit for applying a positive bias voltage to the gate terminal of the high-voltage side FET 2, reference numeral 11 denotes a capacitor for preventing a high-frequency signal from flowing into the bias circuit 14, and reference numeral 8 denotes a predetermined voltage. Power supply, 1
Reference numerals 2 and 13 denote two voltage-dividing resistors that divide the voltage of the power supply device at a predetermined division ratio to generate the positive bias voltage. In the second embodiment, the positive bias voltage is adjusted so that the operation state of the first embodiment shown in FIG. 2 is obtained. The other configuration is the same as that of the first embodiment, and the description is omitted.

In the second embodiment, two FEs
Instead of changing the design of T1 and T2, a positive bias voltage is applied to the high-side FET 2 so that the operating points of the two FETs 1 and 2 are the same as in the first embodiment. As a result, similarly to the first embodiment, the high-frequency signal is efficiently converted by the local signal, and the conversion gain as a mixer is remarkably improved. Amplification modulation can improve intermodulation distortion.

Embodiment 3 FIG. 4 is a circuit diagram showing a configuration of a high-frequency mixer according to Embodiment 3 of the present invention. In the figure, reference numeral 18 denotes a setting circuit for outputting a set value of the interstage voltage VF between the drain terminal of the low-voltage side FET 1 and the source terminal of the high-voltage side FET 2, and 16 and 17 divide the voltage of the power supply device to a predetermined value. Is a division resistor for generating a set value of the inter-stage voltage VF, and comprises an operational amplifier 15 for detecting the inter-stage voltage VF and comparing the detected value with the set value of the inter-stage voltage VF. In order to eliminate the voltage difference between the detected value of the voltage VF and the set value, the high-side FET 2
Is an output adjustment circuit that outputs a DC bias voltage larger than 0 V to the gate terminal of the power supply. The other configuration is the same as that of the second embodiment, and the description is omitted.

In the third embodiment, the high-pressure side FE
Since the positive bias voltage is applied to T2, the same operation and effect as those of the second embodiment can be obtained. Further, in the third embodiment, when the interstage voltage VF fluctuates from a predetermined set value or is set to be deviated due to a process variation of the high voltage side FET 2 or the like, a temperature change of the high voltage side FET 2 or the like. Changes the output voltage so that the output adjustment circuit suppresses the change. Therefore, in the second embodiment, when the threshold voltage Vth2 of the high-side FET 2 decreases due to a variation in the semiconductor process, the low-side FET 1
The voltage VF applied to the signal becomes small, and the high-frequency signal must be converted by relying on the local signal. In the fourth embodiment, even in such a case, a constant conversion efficiency is maintained and the conversion is efficiently performed. Can be performed. In the above description, the combination with the second embodiment has been described, but the same effect can be obtained with the combination with the first embodiment.

Embodiment 4 FIG. FIG. 5 is a circuit diagram showing a configuration of a high-frequency mixer according to Embodiment 4 of the present invention. In the figure, reference numeral 21 denotes a bias circuit for applying a positive bias voltage to the gate terminal of the high-voltage side FET 2, 8 denotes a power supply device for generating a predetermined voltage, and 19 denotes a high-voltage device formed simultaneously with the high-voltage side FET 2 in the same process. This is a setting FET created at the same time in the same semiconductor process as the side FET.
Reference numeral 20 denotes a resistor (voltage generating member) that generates a voltage according to the magnitude of the current. The source terminal and the gate terminal of the setting FET 19 are grounded, so that a predetermined current flows through the resistor. The other configuration is the same as that of the second embodiment, and the description is omitted. The current consumed by the bias circuit 21 is the low voltage side FET 1
And a much smaller current different from the drain current Ids flowing through the high-voltage side FET 2 flows.

Therefore, in the fourth embodiment, the high-pressure side FE
Since the positive bias voltage is applied to T2, the same operation and effect as those of the second embodiment can be obtained. Further, in the fourth embodiment, when the interstage voltage VF fluctuates from a predetermined set value or is set to be deviated due to a process variation of the high-voltage side FET 2 or the like, a temperature change of the high-voltage side FET 2 or the like. Is a setting FET 19 formed by the same process.
Also changes in a similar manner, so that the interstage voltage VF can be stabilized at a predetermined set value. Therefore, in the second embodiment, when the threshold voltage Vth2 of the high-side FET 2 decreases due to a variation in the semiconductor process, the low-side FET 1
The voltage VF applied to the signal becomes small, and the high-frequency signal must be converted by relying on the local signal. In the fourth embodiment, even in such a case, a constant conversion efficiency is maintained and the conversion is efficiently performed. Can be performed. Further, when generating a bias voltage, a specific setting F
Since the ET19 is used, the same function can be realized with a smaller circuit than the circuit configuration shown in the third embodiment. In the above description, the combination with the second embodiment has been described, but the same effect can be obtained with the combination with the first embodiment.

Embodiment 5 FIG. 6 is a circuit diagram showing a configuration of a high-frequency mixer according to Embodiment 5 of the present invention. In the figure, reference numerals 23 and 25 denote matching inductors for cutting low-frequency components contained in high-frequency signals, and these constitute a matching circuit 6 for high-frequency signals. Reference numerals 22 and 24 denote matching inductors for cutting low-frequency components included in the local signal, and these constitute a matching circuit 5 for the local signal. The other configuration is the same as that of the first embodiment, and the description is omitted.

Therefore, these input signals (high-frequency signals,
Even if the local signal includes noise of a relatively low frequency component close to the intermediate frequency signal, the noise is not attenuated by the matching circuits 5 and 6 and input to the FETs 1 and 2. Therefore, in the fifth embodiment, together with the operation and effect of the first embodiment, a local signal source (not shown) connected to the local terminal 41 and a high-frequency signal source (not shown) connected to the high-frequency signal terminal 40 Even if a noise signal in the intermediate frequency band is output from the mixer, the noise in the intermediate frequency band is not mixed with the intermediate frequency signal, and the mixer is a low-noise mixer. In the above description, a combination with the first embodiment has been described.
The same operation and effect can be obtained even in combination with.

Embodiment 6 FIG. FIG. 7 is a circuit diagram showing a configuration of a high-frequency mixer according to Embodiment 6 of the present invention. In the drawing, reference numeral 26 denotes a stabilizing resistor connected to the drain terminal of the high-voltage side FET 2, 27 denotes a stabilizing capacitor 27 connected between the other end of the stabilizing resistor 26 and the ground plane, and 28 denotes a stabilizing capacitor. It is a stabilizing inductor connected between the connection point between the stabilizing resistor 26 and the stabilizing capacitor 27 and the intermediate frequency matching circuit 7, and these constitute a stabilizing circuit 44 having low-pass filter characteristics. The stabilizing capacitor 27 has a sufficiently high impedance at the local frequency, the high-frequency signal frequency, and the intermediate frequency, and has a negligible capacitance value. At a frequency higher than the intermediate frequency, the stabilizing inductor 28 has an impedance. It is set to have a high value.

Therefore, noise or unnecessary signals having a frequency higher than the high-frequency signal frequency or the local frequency are attenuated by the stabilizing resistor 26 and the stabilizing capacitor 27, thereby preventing instability such as oscillation. Further, since the stabilizing circuit 44 has a small loss at the local frequency, the high-frequency signal frequency, and the intermediate frequency, the decrease in the conversion gain by this circuit is suppressed to the minimum necessary. The inductor 28 connected in series to the intermediate frequency matching circuit 7
May also be used as an input section of the intermediate frequency matching circuit 7.

As described above, in the sixth embodiment, the stabilizing circuit is provided between the drain terminal of the high-voltage side FET 2 and the intermediate frequency matching circuit 7 together with the operation and effect of the first embodiment. Stable operation without oscillation. In the above description, the combination with the first embodiment has been described, but the same effect can be obtained with the combination with the second embodiment.

Embodiment 7 FIG. FIG. 8 is a circuit diagram showing a configuration of a high-frequency mixer integrated circuit according to Embodiment 7 of the present invention. In the figure, 5 is a local signal matching circuit, 6 is a high frequency signal matching circuit, 7 is an intermediate frequency signal matching circuit, and 34 is a high frequency mixer integrated circuit. The high frequency mixer integrated circuit 34 includes a mixer main circuit 29 and a plurality of pads 31 and 3 for signal connection.
The semiconductor chip 30 on which the semiconductor chips 2 and 33 are formed, a package 43 covering the semiconductor chip 30, and a plurality of leads 35, 36 and 37 arranged around the package.
And the respective leads 35, 36, 37 and the respective pads 31, 3
2 and 33 and a bonding wire 38 for connecting the wires.

In the seventh embodiment, the matching inductors 23, 22 of the fifth embodiment and the stabilizing inductor 28 of the sixth embodiment are constituted only by the bonding wires 38 and the leads 35, 36, 37.

Therefore, in the high frequency mixer integrated circuit of the seventh embodiment, it is not necessary to separately provide elements for constituting the inductors 23, 22, and 28 above the semiconductor chip 30 and outside the integrated circuit 34. It was possible to achieve miniaturization. In the above description, the combination with the first embodiment has been described, but the same effect can be obtained with the combination with the second embodiment.

Embodiment 8 FIG. FIG. 8 is a circuit diagram showing a configuration of a high-frequency mixer integrated circuit according to Embodiment 8 of the present invention. Each number has been described in the seventh embodiment and will not be described. In the eighth embodiment, the local signal lead 35 is disposed on the opposite side of the package 43 from the high frequency signal lead 36 and the intermediate frequency signal lead 37, and these are allocated in opposite directions.

Therefore, in the eighth embodiment, leakage of a local signal, which is a problem in a high-frequency mixer, into a circuit of a high-frequency signal system or a circuit of an intermediate frequency signal system can be reduced.

The mixer main circuit 29 on the semiconductor chip may have any of the circuit configurations of the first to sixth embodiments.

[0049]

As described above, according to the present invention, the two Fs are set so that the absolute value of the threshold voltage of the high-voltage FET is at least equal to or higher than the knee voltage of the low-voltage FET.
Since the characteristics of the ET are set, the operating point in the bias state can be set substantially near the knee voltage Vknee1 of the low-voltage side FET. Therefore, it is possible to input a local signal having an amplitude that fluctuates the operating point in a wide voltage range, and it is possible to efficiently change the drain-source current Ids with the local signal. Accordingly, the high-frequency signal can be efficiently frequency-converted. Further, since the high-frequency signal is input to the high-side FET, there is an effect that a sufficient operating voltage can be secured and the intermodulation distortion (third-order distortion) characteristics can be improved.

According to the present invention, since the DC bias voltage larger than 0 V is applied to the gate terminal of the high-side FET, the threshold voltage Vt of the high-side FET is increased.
h2 becomes higher, and the operating point in the bias state can be set substantially near the knee voltage Vknee1 of the low-voltage side FET. Therefore, it is possible to input a local signal having an amplitude that fluctuates the operating point in a wide voltage range, and it is possible to efficiently change the drain-source current Ids with the local signal. Accordingly, the high-frequency signal can be efficiently frequency-converted. Further, since the high-frequency signal is input to the high-voltage side FET, a sufficient operating voltage can be ensured and the intermodulation distortion (third-order distortion) characteristics can be improved.
Furthermore, since no restrictions are imposed on the threshold voltage of the high-side FET and the low-side FET,
The high-frequency mixer can be configured using FETs that emphasize other characteristics such as noise characteristics, and as a result, high performance and multi-functionality can be achieved.

According to the present invention, the setting circuit for outputting the set value of the inter-stage voltage between the drain terminal of the low-voltage side FET and the source terminal of the high-voltage side FET, the inter-stage voltage is detected and the inter-stage voltage is detected. An output adjustment circuit that outputs a DC bias voltage greater than 0 V to the gate terminal of the high-side FET so that there is no voltage difference between the detected value of the inter-stage voltage and the set value as compared with the set value of the voltage; Is provided, the inter-stage voltage VF is reduced by the knee voltage Vkn of the low-voltage side FET due to process variations and temperature changes.
It can be prevented from becoming smaller than e1, and there is an effect that a stable operating point can be obtained regardless of process variations and temperature changes.

According to the present invention, the setting FET which is simultaneously formed in the same semiconductor process as the high-voltage side FET and whose source terminal and gate terminal are connected to the low-voltage terminal of the power supply.
And a setting resistor connected between the high-voltage terminal of the power supply and the drain terminal of the setting FET. The voltage at the connection point between the drain terminal of the setting FET and the setting resistor is set to a high voltage. A bias circuit that outputs a DC bias voltage to the gate terminal of the side FET is provided to prevent the interstage voltage VF from becoming lower than the knee voltage of the low-voltage side FET due to process variations. Thus, stable operation can be performed regardless of process variations. Further, there is an effect that the circuit can be realized with a smaller circuit than when a bias circuit is configured by the setting circuit and the output adjustment circuit.

According to the present invention, a matching circuit having a high-pass filter characteristic is connected to the gate terminal of the high-voltage side FET and / or the gate terminal of the low-voltage side FET, and the high-frequency signal and / or the local signal pass through the high-pass filter. Since the noise signal having a frequency close to the intermediate frequency input from the local signal input terminal and the high frequency signal input terminal is attenuated by the high-pass filter, the noise signal is input to the predetermined gate terminal. The signal is not superimposed on the intermediate frequency signal and output from the output terminal. Therefore, there is an effect that a low-noise high-frequency mixer can be obtained without obstructing the operation of generating the intermediate frequency signal from the high-frequency signal and the local signal.

According to the present invention, the matching circuit is formed using the matching inductor, and all or a part of the matching inductor is formed of the bonding wire and / or the bonding wire.
Alternatively, since it is composed of the leads, the size of the inductor outside the chip or the package can be reduced, so that there is an effect that the performance can be improved or the size can be reduced.

According to the present invention, since the stabilizing circuit having the low-pass filter characteristic is provided at the drain terminal of the high-voltage side FET, the local signal or the high-frequency signal higher in frequency than the intermediate frequency signal is attenuated while the intermediate frequency signal is attenuated. Signals can be output efficiently. Therefore, the output does not oscillate due to a high frequency signal, etc.
A stable operation can be performed.

According to the present invention, the stabilizing circuit includes the stabilizing resistor having one end connected to the drain terminal of the high-voltage side FET, and the other end of the stabilizing resistor and the low-voltage terminal of the power supply or the ground plane. A connected stabilizing capacitor, and a stabilizing inductor having one end connected to a connection point between the stabilizing resistor and the stabilizing capacitor and outputting an intermediate frequency signal from the other end. Alternatively, since a part of the inductor is constituted by bonding wires and / or leads, the size of the inductor outside the chip or the package can be reduced, and there is an effect that the performance can be improved or the size can be reduced accordingly.

According to the present invention, the local signal lead for inputting the local signal and the high frequency signal lead for inputting the high frequency signal are assigned to the leads of the package in opposite directions. One signal does not interfere with the other signal due to crosstalk or the like, and there is an effect that a local signal can be reduced from leaking into a high-frequency signal circuit or an intermediate frequency circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-frequency mixer according to Embodiment 1 of the present invention.

FIG. 2 is a characteristic diagram of the high-frequency mixer of FIG.

FIG. 3 is a circuit diagram of a high-frequency mixer according to Embodiment 2 of the present invention.

FIG. 4 is a circuit diagram of a high-frequency mixer according to Embodiment 3 of the present invention.

FIG. 5 is a circuit diagram of a high-frequency mixer according to Embodiment 4 of the present invention.

FIG. 6 is a circuit diagram of a high-frequency mixer according to Embodiment 5 of the present invention.

FIG. 7 is a circuit diagram of a high-frequency mixer according to Embodiment 6 of the present invention.

FIG. 8 is a view illustrating a seventh embodiment and an eighth embodiment of the present invention;
1 is a circuit diagram of a high frequency mixer integrated circuit according to the present invention.

FIG. 9 is a circuit diagram of a conventional high-frequency mixer.

FIG. 10 is a characteristic diagram of the high-frequency mixer of FIG. 9;

[Explanation of symbols]

1 low voltage side field effect transistor, 2 high voltage side field effect transistor, 5, 6 matching circuit, 8 power supply, 14
Bias circuit, 15 output adjustment circuit, 18 setting circuit,
19 setting field-effect transistor, 20 setting resistor, 22, 23, 24, 25 matching inductor, 26
Stabilizing resistor, 27 Stabilizing capacitor, 28 Stabilizing inductor, 35, 36, 37 Lead, 38 Bonding wire, 44 Stabilizing circuit.

Continued on the front page. (72) Inventor Noriko Ogata 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Japan Mitsubishi Electric Corporation (72) Inventor Masayoshi Ono 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Mitsubishi Inside Electric Co., Ltd. (72) Inventor Yoshitada Iyama 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. Inside (72) Inventor Yukio Miyazaki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (9)

[Claims] 1. A high-voltage field-effect transistor comprising two field-effect transistors connected in cascade between a high-voltage terminal and a low-voltage terminal of a power supply. A high-frequency mixer that outputs an intermediate frequency signal from the drain terminal of the two field-effect transistors such that the absolute value of the threshold voltage of the high-voltage field-effect transistor is at least equal to or greater than the knee voltage of the low-voltage field-effect transistor. A high-frequency mixer which sets characteristics of a transistor, inputs a high-frequency signal to a gate terminal of the high-voltage side field-effect transistor, and inputs a local signal to a gate terminal of the low-voltage side field-effect transistor. 2. A high-voltage-side field-effect transistor having two field-effect transistors connected in cascade between a high-voltage terminal and a low-voltage terminal of a power supply. A high-frequency mixer that outputs an intermediate frequency signal from the drain terminal of the high-frequency side field-effect transistor, applies a DC bias voltage greater than 0 V by a bias circuit to the gate terminal of the high-voltage side field-effect transistor, and inputs the high-frequency signal; A high-frequency mixer, wherein a gate terminal of the low-voltage side field-effect transistor is grounded and a local signal is input. 3. A setting circuit for outputting a set value of an inter-stage voltage between a drain terminal of a low-voltage side field-effect transistor and a source terminal of a high-voltage side field-effect transistor; A DC bias voltage greater than 0 V is output to the gate terminal of the high-voltage field-effect transistor so that the voltage difference between the detected value of the inter-stage voltage and the set value is eliminated as compared with the set value of the inter-stage voltage. 3. The high-frequency mixer according to claim 1, further comprising a bias circuit including an output adjustment circuit. 4. A setting field-effect transistor which is simultaneously formed in the same semiconductor process as a high-voltage side field-effect transistor and has a source terminal and a gate terminal connected to a low-voltage terminal of a power supply; A setting resistor connected between the drain terminal of the field effect transistor for setting and the voltage at the connection point between the drain terminal of the setting field effect transistor and the setting resistor. 3. The high frequency mixer according to claim 1, further comprising a bias circuit for outputting a DC bias voltage to the gate terminal. 5. A matching circuit having a high-pass filter characteristic is connected to the gate terminal of the high-voltage side field-effect transistor and / or the gate terminal of the low-voltage side field-effect transistor, and the high-frequency signal and / or the local signal pass through the high-pass filter. 3. The high-frequency mixer according to claim 1, wherein the signal is input to a predetermined gate terminal via the input terminal. 6. The high frequency mixer according to claim 5, wherein the matching circuit is configured using a matching inductor, a package covering the high frequency mixer, a plurality of leads disposed around the package, and A high-frequency mixer integrated circuit having a bonding wire for connecting a lead to the high-frequency mixer, wherein the matching inductor is entirely or partially formed of a bonding wire and / or a lead. 7. The high-frequency mixer according to claim 1, wherein a stabilizing circuit having a low-pass filter characteristic is provided at a drain terminal of the high-voltage side field-effect transistor. 8. A stabilizing circuit comprising: a stabilizing resistor having one end connected to a drain terminal of a high-voltage side field effect transistor;
One end is connected to the stabilizing capacitor connected between the other end of the stabilizing resistor and the low voltage terminal of the power supply or the ground plane, and one end is connected to the connection point between the stabilizing resistor and the stabilizing capacitor, and the other end is intermediate from the other end. 8. The high-frequency mixer according to claim 7, comprising a stabilizing inductor for outputting a frequency signal, a package covering the high-frequency mixer, a plurality of leads disposed around the package, and connecting each lead to the high-frequency mixer. A high-frequency mixer integrated circuit, characterized in that the stabilizing inductor is entirely or partially composed of bonding wires and / or leads. 9. A high-frequency mixer according to claim 1 or 2, a package covering the high-frequency mixer, and a local signal which is disposed around the package and receives a local signal to the high-frequency mixer. A high-frequency mixer integrated circuit comprising: a lead; and a high-frequency signal lead, which is disposed around the package in a direction opposite to the local signal lead and receives a high-frequency signal to be input to the high-frequency mixer. .