JPH11289488A - System adjustment method/device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system where even a low speed test signal generating source can generate a test signal at a signal processing trace rate and the circuit scale and the power consumption are reduced by using a signal processing memory and a test signal memory in common. SOLUTION: At operation of a system, an input signal is written in a memory 5 at a digital signal processing rate and read from the memory 5 at a digital signal processing rate, a signal processing circuit 6 applies prescribed signal processing to the signal in real time. At the adjustment of the system, the input signal is written in the memory 5 at a lower rate than the digital signal processing rate and read from the memory 5 at this digital signal processing rate, the signal processing circuit 6 applies prescribed signal processing to the signal to adjust the system. Thus, a test signal at a signal processing rate is generated from a low speed test signal generating source and the circuit scale and the power consumption are reduced by using a signal processing memory and a test signal memory in common.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to generation of a test signal used for adjusting a system of a television camera device or the like.

[0002]

2. Description of the Related Art Conventionally, digital signal processing, N
As shown in FIG. 7, a TSC (National Television System Committee) television camera device has a lens 7
The image captured by the CCD is
ice) 8, which is converted into an electric signal,
The signal is converted from an analog signal to a digital signal by a DC (Analog to Digital Converter) 9. The converted digital signal is subjected to various types of image processing by the image processing circuit 10 and then converted to a DAC (Digital to Analog Converter) 1.
1, the video signal 12 is output after being converted back to an analog signal. With this configuration, the image processing circuit 10 has a circuit configuration as shown in FIG.
Normally, the system is in the operating state as shown in FIG. 5, and performs various image processing. When making system adjustments,
As shown in FIG. 6, the test data TD generated by the test signal generation circuit 1 of FIG.
The system is in a system adjustment state in which adjustment of the signal processing circuit 6 and adjustment of a subsequent system connected to the video output 12 are performed.

[0003] When the system is operating, as shown in FIGS.
Then, a control signal (write clock FK, write enable FE, write reset FR which is the timing shown in FIG. 5) for writing the input data ID to the frame memory 5 is generated from the input clock IC and the input data ID is written. Further, the signal processing circuit 6 reads a read control signal (read clock RK, read enable RE, timing shown in FIG. 5) from the system synchronization signal SP and the system clock SC.
A read reset RR is generated, and the held data MO is read from the frame memory 5. At this time, the selection circuit 3 selects the held data MO for output. The selected data MI is subjected to signal processing by the signal processing circuit 6 and then output as output data OD. As a result, the input data signal ID is stored in the frame memory 5 in the system synchronization signal SP.
After that, various image processes are performed by the signal processing circuit 6.

On the other hand, at the time of system adjustment, as shown in FIGS.
Then, test data TD having the timing shown in FIG. 6 is generated. At this time, the selection circuit 3 outputs the test data TD to the output.
Is selected, the selected data MI is subjected to signal processing by the signal processing circuit 6, and then output as output data OD, and adjustment is performed. Thus, the test signal generation circuit 1
Has a configuration in which the system clock SC is supplied and operates. Here, a 400,000 pixel CCD (Charge Coupl
ed Device), the system clock SC and the input clock IC are 14.318.
MHz. In recent years, HDTV (High Definition Telev
Television camera devices capable of imaging in the (ision) method have come out, and in the case of a system that drives and operates a 2 million pixel CCD, the system clock SC and the input clock IC are 74.25 MHz, It is expected that the speed of the system clock SC and the input clock IC will increase in the future.

[0005]

In the above conventional apparatus, H
When trying to realize the DTV system, the input clock IC
Is 74.25 MHz, so the test signal generation circuit 1 also
Must operate at 74.25 MHz. For this reason,
It is necessary to increase the speed of the test signal generating circuit 1, which causes a problem that the circuit scale increases, the cost and the board area increase, and a problem that the power consumption increases due to the increase in the clock speed and the circuit scale. . The present invention improves upon the conventional method, solves these problems, enables the generation of a test signal at a signal processing rate even with a low-speed test signal source, and provides a signal processing memory and a test signal memory. An object of the present invention is to realize a system capable of reducing the circuit scale and power consumption by sharing.

[0006]

According to the present invention, in order to achieve the above object, an input signal is written into a memory at a digital signal processing rate and read at a digital signal processing rate during operation of a system. When the system is adjusted, a test signal is written to the memory at a predetermined rate lower than the digital signal processing rate, read at the digital signal processing rate, and read by the signal processing circuit. Is performed to perform system adjustment. A means for selecting and outputting one of an input signal and a test signal according to a state of the system; a memory means for holding the selected output signal;
Means for writing the input signal to the memory means at a digital signal processing rate, generating the test signal at a predetermined rate lower than the digital signal processing rate and writing the test signal to the memory means, and means for converting the signal held in the memory means into a digital signal A signal processing means for reading out the digital signal at a processing rate and performing digital signal processing; performing a real-time signal processing for reading out the input signal held in the memory means at a digital signal processing rate and performing signal processing when the system is operating; At the time of adjustment, a system adjustment for reading out the test signal held in the memory means at a digital signal processing rate and performing signal processing is performed. As a result, it is possible to generate a test signal of a signal processing rate at a low-speed test signal generation source, share a signal processing memory and a test signal memory, and reduce the circuit scale and power consumption.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, as one embodiment of the present invention,
The configuration and operation of the system will be described with reference to FIG.
Reference numeral 1 denotes a test data TD and a memory control write clock T based on a system synchronization signal SP and a test clock TC.
K, a write enable TE, a test signal generation circuit for generating a write reset TR, and a memory control write clock F based on an input synchronization signal IP and an input clock IC.
K, a write sync enable circuit FE, a frame sync control circuit for generating a write reset FR, and a test control signal TP which outputs one of the input data ID and test data TD.
And a selection circuit for selecting as
Is a memory control signal including a write clock FK, a write enable FE, and a write reset FR, and a write clock TK, a write enable TE, and a write reset T.
A selection circuit for selecting one of the memory control signals consisting of R by the test control signal TP and outputting it as a memory control write clock WK, a write enable WE, and a write reset WR. WK, write enable WE, write reset WR
, The memory control read clock RK, the read enable RE, and the read reset RR.
A frame memory 6 for outputting O and a signal processing circuit 6 for performing various signal processing.

ID is input video data, IP is an input video synchronization signal, IC is an input video sampling clock, TC is a clock for driving the test signal generating circuit 1, and TP is a system. A control signal for setting the operation mode or the adjustment mode, TD is test data for adjusting the system, TK is a clock signal for writing and controlling the test data TD in the memory, and TE is an enable signal for writing and controlling the test data TD in the memory. , TR is a reset signal for writing and controlling the test data TD to the memory, FK is a clock signal for writing and controlling the input data ID to the memory, FE is an enable signal for writing and controlling the input data ID to the memory, and FR is a signal for storing the input data ID in the memory. Reset signal for writing control to
Is a selection data selected by the selection circuit 3, WK is a clock signal for writing and controlling the selection data MI in the memory, WE
Is an enable signal for controlling the writing of the selected data MI to the memory, WR is a reset signal for controlling the writing of the selected data MI to the memory, MO is the held data held in the frame memory 5, and RK is the read control of the held data MO from the memory. A clock signal, RE is an enable signal for controlling readout of the retained data MO from the memory, RR is a reset signal for controlling readout of the retained data MO from the memory, OD is output data of video subjected to various signal processing by the signal processing circuit 6, SP is a system synchronization signal for driving the system, and SC is a system clock for driving the system.

The test signal generating circuit 1 generates test data TD based on a system synchronization signal SP and a test clock TC, and simultaneously generates a write clock TK, a write enable TE, and a write reset TR for controlling the writing of the test data TD into the frame memory 5. Generate. The frame synchronization control circuit 2 receives the input synchronization signal IP and the input clock I
C, a write clock FK for controlling writing of the input data ID into the frame memory 5, a write enable FE,
Generate a write reset FR. When the test control signal TP indicates the operation mode of the system, the selection circuits 3 and 4 provide the input data ID for the selected data MI, the write clock FK for the write clock WK, the write enable FE for the write enable WE, A write reset FR is output to the write reset WR, and when the test control signal TP indicates the system adjustment mode, the test data TD is selected for the selected data MI, the write clock TK is set for the write clock WK, and the write clock TK is set for the write enable WE. Write enable TE, write reset T for write reset WR
Output R. The frame memory 5 writes the selected selection data MI by the write clock WK, the write enable WE, and the write reset WR from the selection circuit 4. The signal processing circuit 6 generates a read clock RK for memory control, a read enable RE, and a read reset RR based on the system synchronization signal SP and the system clock SC, reads the retained data MO from the frame memory 5, and outputs various images to the read data. Processing is performed, and output data OD is output.

Here, when the system is operating, as shown in FIG. 3, the input data (video data) ID is selected by the selection circuit 3 and the selected data (video data) MI is stored in the frame memory 5.
Is entered as At this time, the frame synchronization control circuit 2 uses the input synchronization signal IP and the input clock IC to
A control write clock FK, a write enable FE, and a write reset FR for writing the input data ID to the frame memory 5 are generated, and the corresponding write clock WK, write enable WE, and write reset WR are selected and output from the selection circuit 4. The input data (video data) ID is written to the frame memory 5. Signal processing circuit 6
Generates a read control read clock RK, a read enable RE, and a read reset RR based on the system synchronization signal SP and the system clock SC, reads the held data (video data) MO from the frame memory 5,
After performing various signal processing, output data (video data) O
Signal processing is performed by outputting as D.

On the other hand, during system adjustment, as shown in FIG. 4, the test signal generating circuit 1
The test data TC, the test clock TD, the write clock TK, the write enable TE, and the write reset TR are generated by the test clock TC. The test data TD is selected by the selection circuit 3 and is input to the frame memory 5 as the selected data MI. At this time, in the selection circuit 4, the input write clock TK, write enable TE, and write reset TR
With the corresponding write clock WK and write enable W
E, output as a write reset WR, and test data TD is written to the frame memory 5. Here, based on the system synchronization signal SP and the system clock SC, the signal processing circuit 6 reads the read control read clock RK,
Generate read enable RE and read reset RR,
The held data (test data) MO is read from the frame memory 5 and subjected to various kinds of signal processing to output data O.
The system is adjusted by outputting D. As described above, the test signal generation circuit 1 is configured to operate based on the test clock TC, and the test clock TC is set to a clock slower than the system clock SC (for example, the system clock: 74.25 MHz, the test clock: 1).
Even if data is written to the frame memory 5 using (4.318 MHz), reading from the frame memory 5 can be performed by the system clock SC.

As described above, during system operation, real-time signal processing is performed by writing input signals to the frame memory and performing signal processing while reading from the frame memory at a digital signal processing rate. The test signal is written at a predetermined rate lower than the signal processing rate, the signal processing is performed while reading from the frame memory at the signal processing rate, and system adjustment can be performed. The circuit scale and power consumption are reduced by enabling generation of a test signal and sharing a signal processing frame memory and a test signal frame memory. In this embodiment, a camera system has been described as an example, and a system that drives and operates a 2 million pixel CCD in the HDTV system has been described. However, the present invention is not limited to this, and an NTSC system that drives a high pixel CCD, The present invention can be similarly applied to the EDTV2 system and a system with higher definition than the HDTV system expected in the future, and also applicable to a system other than a camera system which uses a memory and performs signal processing.

[0013]

According to the present invention, a test signal can be generated at a signal processing rate even with a low-speed test signal generation source.
Further, by sharing the signal processing memory and the test signal memory, the circuit scale and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a timing chart showing operation timing when the system according to the present invention is operated.

FIG. 4 is a timing chart showing operation timings at the time of system adjustment according to the present invention.

FIG. 5 is a timing chart showing operation timing when a conventional system is operated.

FIG. 6 is a timing chart showing operation timing at the time of conventional system adjustment.

FIG. 7 is a block diagram showing a configuration of a general camera system.

[Explanation of symbols]

1: test signal generation circuit, 2: frame sync control circuit, 3, 4: selection circuit, 5: frame memory, 6: signal processing circuit, ID: input data, IP: input synchronization signal, I
C: input clock, TC: test clock, TP: test control signal, TD: test data, TK: write clock, TE: write enable, TR: write reset,
FK: write clock, FE: write enable, F
R: write reset, MI: select data, WK: write clock, WE: write enable, WR: write reset, MO: held data, RK: read clock, R
E: Read enable, RR: Read reset, OD:
Output data, SP: system synchronization signal, SC: system clock.

Claims (3)

[Claims] When operating a system, an input signal is written to a memory at a digital signal processing rate, read at a digital signal processing rate, a predetermined signal processing is performed in a signal processing circuit to perform real-time signal processing, and system adjustment is performed. At the time, a test signal is written to the memory at a predetermined rate lower than the digital signal processing rate, read at the digital signal processing rate, and the signal processing circuit performs predetermined signal processing to perform system adjustment. How to adjust the system. 2. A means for selecting and outputting one of an input signal and a test signal in accordance with a state of a system, a memory means for holding the selected output signal, and converting the input signal at a digital signal processing rate. Means for writing to the memory means, for generating the test signal at a predetermined rate lower than the digital signal processing rate and writing to the memory means, and for reading the signal held in the memory means at the digital signal processing rate for digital signal processing. Performing a real-time signal processing for reading out the input signal held in the memory means at a digital signal processing rate and performing signal processing when the system is operating;
The system adjustment device performs system adjustment for reading out the test signal held in the memory means at a digital signal processing rate and performing signal processing at the time of system adjustment. 3. The system adjustment device according to claim 2, wherein the system adjustment device is applied to system adjustment of a television camera device.