JPH11288934A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH11288934A
JPH11288934A JP9038998A JP9038998A JPH11288934A JP H11288934 A JPH11288934 A JP H11288934A JP 9038998 A JP9038998 A JP 9038998A JP 9038998 A JP9038998 A JP 9038998A JP H11288934 A JPH11288934 A JP H11288934A
Authority
JP
Japan
Prior art keywords
metal film
mos
light
film
type transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9038998A
Other languages
Japanese (ja)
Inventor
Tetsuo Shioura
哲郎 塩浦
Shigeto Inoue
成人 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP9038998A priority Critical patent/JPH11288934A/en
Publication of JPH11288934A publication Critical patent/JPH11288934A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To shield even oblique light by forming a second metal film for covering an entire semiconductor element on a first metal film, while sandwiching an insulation film. SOLUTION: For example, an MOS-type transistor 2 consists of a gate electrode, a source, and a drain on a semiconductor substrate 1, and metal wiring for electrically connecting them. A first metal film 4 that is connected directly to the semiconductor substrate via a contact hole 3 is provided around the MOS-type transistor 2. Also, a second metal film 6 is provided on the MOS-type transistor 2 via an insulation film 7, and the first metal film 4 and the second metal film 6 are connected by a through hole 5. In this case, to prevent oblique light from entering, the contact hole 3 and a through-hole 5 are arranged so that the surrounding of the MOS-type transistor 2 will not be interrupted. In this manner, by installing a lower layer metal film around the semiconductor element, light is shielded and light leakage is reduced, thus stably operating an element.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は半導体集積回路、特に
液晶駆動用のドライバーICや電源用IC等ガラス基板
に直接実装する半導体集積回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit directly mounted on a glass substrate such as a driver IC for driving a liquid crystal or an IC for a power supply.

【0002】[0002]

【従来の技術】例えばCOG(Chip On Glas
s)の様に半導体集積回路をガラス基板に直接実装する
技術の場合には、液晶パネルを透過して光が侵入するた
め誤動作を起こしやすく、半導体素子上を金属膜で覆っ
て遮光し、誤動作を防止している。
2. Description of the Related Art For example, COG (Chip On Glass)
In the case of the technique of directly mounting a semiconductor integrated circuit on a glass substrate as in s), light penetrates through the liquid crystal panel, which easily causes malfunctions. Has been prevented.

【0003】従来の半導体集積回路における遮光の一例
を図3に示す。図3(a)は断面構造図、図3(b)は
平面レイアウト図である。図において、MOS型トラン
ジスタ2の上全体を覆う第2の金属膜6を形成し、上か
らの光を遮光している。
FIG. 3 shows an example of light shielding in a conventional semiconductor integrated circuit. FIG. 3A is a cross-sectional structure diagram, and FIG. 3B is a plan layout diagram. In the figure, a second metal film 6 covering the entire top of the MOS transistor 2 is formed to shield light from above.

【0004】[0004]

【発明が解決しようとする課題】半導体素子全体を上層
の金属膜で覆っても、斜め方向からの光の場合、金属膜
の終端部と半導体基板の間に隙間が生じてしまい、光が
侵入して好ましくなかった。
Even when the entire semiconductor element is covered with an upper metal film, in the case of light from an oblique direction, a gap is formed between the terminal portion of the metal film and the semiconductor substrate, and light enters. Was not preferred.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、本発明では半導体素子上だけでなく、横にも下層の
金属膜を設けることにより斜めからの光に対しても遮光
出来るようにした。上述した構成により、斜めからの光
に対しても半導体素子の誤動作を防止出来る。
In order to solve the above-mentioned problems, in the present invention, a lower metal film is provided not only on a semiconductor element but also laterally so that light can be shielded from oblique light. did. With the above-described configuration, malfunction of the semiconductor element can be prevented even for oblique light.

【0006】[0006]

【発明の実施の形態】図1は本発明の第1実施例を示し
ており、図1(a)は断面構造図、図1(b)は平面レ
イアウト図である。本発明では、半導体基板1上に設け
られたゲート電極、ソース、ドレイン、そしてこれらを
電気接続する金属配線からなるMOS型トランジスタ2
において、このMOS型トランジスタの周囲にコンタク
トホール3を介して直接半導体基板に接続したアルミニ
ウムなどからなる第1の金属膜4と、MOS型トランジ
スタ上に絶縁膜7を介して設けられたアルミニウムなど
からなる第2の金属膜6と、第1の金属膜と第2の金属
膜をスルーホール5で接続した構造となる。ここで斜め
からの光の侵入を防止するために、コンタクトホール3
とスルーホール5は図1(b)の様に半導体素子の周囲
を途切れない様に配置した方が良い。
FIG. 1 shows a first embodiment of the present invention. FIG. 1 (a) is a sectional structural view, and FIG. 1 (b) is a plan layout view. According to the present invention, a MOS transistor 2 comprising a gate electrode, a source, a drain provided on a semiconductor substrate 1 and a metal wiring for electrically connecting them is provided.
A first metal film 4 made of aluminum or the like directly connected to the semiconductor substrate via a contact hole 3 around the MOS transistor and an aluminum or the like provided on the MOS transistor via an insulating film 7 The second metal film 6 has a structure in which the first metal film and the second metal film are connected through the through hole 5. Here, in order to prevent light from entering obliquely, contact holes 3
It is preferable that the through holes 5 are arranged so as not to be interrupted around the semiconductor element as shown in FIG.

【0007】もちろんコンタクトホール3とスルーホー
ル5の位置関係が逆であっても同等の効果がある。また
第1の金属膜4は、コンタクトホール3を介して半導体
基板に接続されて無くても効果はある。MOSトランジ
スタのソース、ドレイン及びゲート電極を電気接続する
金属配線と、第1の金属膜が同じ積層膜からなる場合等
は、コンタクトホール部と金属膜の距離を短くした方が
良い。
Of course, the same effect is obtained even if the positional relationship between the contact hole 3 and the through hole 5 is reversed. The first metal film 4 is effective even if it is not connected to the semiconductor substrate via the contact hole 3. In the case where the metal wiring for electrically connecting the source, drain and gate electrodes of the MOS transistor and the first metal film are formed of the same laminated film, the distance between the contact hole and the metal film is preferably shortened.

【0008】図2に本発明の第2実施例を示す。第1実
施例と同様に半導体基板上に設けられたMOS型トラン
ジスタ2において、このMOS型トランジスタの周囲に
設けられた多結晶シリコンなどからなるゲート電極膜8
と、該ゲート電極膜8へのコンタクトホール3を介して
接続したアルミニウムなどからなる第1の金属膜4と、
MOS型トランジスタ上に絶縁膜7を介して設けられた
アルミニウムなどからなる第2の金属膜6と、第1の金
属膜と第2の金属膜をスルーホール5で接続した構造と
なる。この実施例でも第1実施例と同様に遮光の効果が
ある。
FIG. 2 shows a second embodiment of the present invention. In the MOS transistor 2 provided on the semiconductor substrate as in the first embodiment, the gate electrode film 8 made of polycrystalline silicon or the like provided around the MOS transistor.
And a first metal film 4 made of aluminum or the like connected to the gate electrode film 8 via the contact hole 3,
A structure in which a second metal film 6 made of aluminum or the like provided on a MOS transistor via an insulating film 7 and a first metal film and a second metal film are connected through a through hole 5 is provided. This embodiment also has a light shielding effect as in the first embodiment.

【0009】[0009]

【発明の効果】以上説明したように、本発明は半導体素
子周辺に下層の金属膜を設置することによって遮光し、
漏れ光を低減して素子の安定動作を実現する効果があ
る。
As described above, the present invention shields light by providing a lower metal film around a semiconductor device.
This has the effect of reducing leakage light and realizing stable operation of the element.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は本発明の半導体集積回路の第1実施例を
示し、図1(a)は断面構造図、図2(b)は平面レイ
アウト図である。
FIGS. 1A and 1B show a first embodiment of a semiconductor integrated circuit according to the present invention. FIG. 1A is a sectional structural view, and FIG. 2B is a plan layout view.

【図2】図2は本発明の第2実施例の断面構造図を示
す。
FIG. 2 shows a sectional structural view of a second embodiment of the present invention.

【図3】図3は従来技術の例を示し、図3(a)は断面
構造図、図3(b)は平面レイアウト図である。
FIGS. 3A and 3B show an example of the prior art, in which FIG. 3A is a sectional structural view, and FIG.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 半導体素子(MOS型トランジスタ) 3 コンタクトホール 4 第1金属膜 5 スルーホールゲート電極膜 6 第2金属膜 7 絶縁膜 8 ゲート電極膜 Reference Signs List 1 semiconductor substrate 2 semiconductor element (MOS transistor) 3 contact hole 4 first metal film 5 through-hole gate electrode film 6 second metal film 7 insulating film 8 gate electrode film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路において、半導体素子の
周囲に設けられた第1の金属膜と、絶縁膜を挟んで前記
第1の金属膜の上に配置された半導体素子の上全体を覆
う第2の金属膜と、該絶縁膜に設けられたスルーホール
により第1の金属膜と第2の金属膜が接続された構造を
特徴とする半導体集積回路。
In a semiconductor integrated circuit, a first metal film provided around a semiconductor element and a first metal film covering an entirety of the semiconductor element disposed on the first metal film with an insulating film interposed therebetween are provided. 2. A semiconductor integrated circuit having a structure in which a second metal film is connected to a first metal film and a second metal film by through holes provided in the insulating film.
JP9038998A 1998-04-02 1998-04-02 Semiconductor integrated circuit Pending JPH11288934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9038998A JPH11288934A (en) 1998-04-02 1998-04-02 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9038998A JPH11288934A (en) 1998-04-02 1998-04-02 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH11288934A true JPH11288934A (en) 1999-10-19

Family

ID=13997236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9038998A Pending JPH11288934A (en) 1998-04-02 1998-04-02 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH11288934A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006216683A (en) * 2005-02-02 2006-08-17 Seiko Epson Corp Semiconductor device
JP2006295045A (en) * 2005-04-14 2006-10-26 Seiko Epson Corp Semiconductor device
US7285817B2 (en) 2004-09-10 2007-10-23 Seiko Epson Corporation Semiconductor device
JP2008113035A (en) * 2008-01-28 2008-05-15 Seiko Epson Corp Semiconductor device
JP2008147695A (en) * 2008-01-28 2008-06-26 Seiko Epson Corp Semiconductor device
JP2008147694A (en) * 2008-01-28 2008-06-26 Seiko Epson Corp Semiconductor device
JP2008153683A (en) * 2008-01-25 2008-07-03 Seiko Epson Corp Semiconductor device
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7285817B2 (en) 2004-09-10 2007-10-23 Seiko Epson Corporation Semiconductor device
CN100409426C (en) * 2004-09-10 2008-08-06 精工爱普生株式会社 Semiconductor device
JP2006216683A (en) * 2005-02-02 2006-08-17 Seiko Epson Corp Semiconductor device
JP2006295045A (en) * 2005-04-14 2006-10-26 Seiko Epson Corp Semiconductor device
JP4626373B2 (en) * 2005-04-14 2011-02-09 セイコーエプソン株式会社 Semiconductor device
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors
US8999764B2 (en) * 2007-08-10 2015-04-07 International Business Machines Corporation Ionizing radiation blocking in IC chip to reduce soft errors
US10784200B2 (en) 2007-08-10 2020-09-22 International Business Machines Corporation Ionizing radiation blocking in IC chip to reduce soft errors
JP2008153683A (en) * 2008-01-25 2008-07-03 Seiko Epson Corp Semiconductor device
JP2008113035A (en) * 2008-01-28 2008-05-15 Seiko Epson Corp Semiconductor device
JP2008147695A (en) * 2008-01-28 2008-06-26 Seiko Epson Corp Semiconductor device
JP2008147694A (en) * 2008-01-28 2008-06-26 Seiko Epson Corp Semiconductor device

Similar Documents

Publication Publication Date Title
JP2001272659A (en) Liquid crystal display device
KR960015020A (en) Display
KR20020013774A (en) Thin film semiconductor device and liquid crystal display unit, and fabrication methods thereof
JPH11305681A (en) Display device
JPH11288934A (en) Semiconductor integrated circuit
KR100487950B1 (en) Semiconductor device having a contact hole disposed on a gate electrode overlapped with an active region
US5581382A (en) Liquid crystal display device having connection pads insulated by double layered anodic oxide material
CN110265440A (en) Display panel and preparation method thereof
TWI400545B (en) Display panel
JPH11345977A (en) Semiconductor device
JP2004311832A (en) Semiconductor device
EP1478971B1 (en) Liquid crystal display device
KR970072343A (en) Tape carrier package and liquid crystal display including the tape carrier package
JPH10170933A (en) Liquid crystal display device
JP4257526B2 (en) Semiconductor device
JP3223394B2 (en) Manufacturing method of liquid crystal display device
JPH02283062A (en) Semiconductor device
JPH0666412B2 (en) Stacked semiconductor integrated circuit
JPH10253991A (en) Liquid crystal display device
JP2006286689A (en) Terminal structure and its bonding structure
KR20080044986A (en) Array substrate and method of manufaturing the same
JP2022090361A (en) Semiconductor device and manufacturing method thereof
JPH07161998A (en) Thin-film transistor device
KR20000003318A (en) Liquid crystal display unit having improving aperature ratio
JP2000235195A (en) Active matrix substrate, process for producing active matrix substrate and process for producing liquid crystal display device