JPH11274512A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to improve integration, along with good reliability in transistor. SOLUTION: In a thin film transistor, an n-type transistor 21 is formed on a transparent insulating substrate 1, and a p-type transistor 22 is formed with a gate insulating film 5. An inner drain/source end of an n-type transistor 21 is self-aligned by an outer drain/source end. An LDD region 7 is formed between the inner drain/source end and a channel region 31 in the n-type transistor 21. Since these transistors 21 and 22 are overlapped vertically, the integration can be improved. In addition, the n-type transistor has the LDD region, so a variation in threshold caused by hot electrons can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming a thin film transistor on a substrate, for example, a thin film transistor used for a liquid crystal display device or the like.

[0002]

2. Description of the Related Art With the spread of notebook computers, liquid crystal display devices having a high resolution and a large screen size have been developed. Further, in order to reduce cost and mounting area, a technique has been proposed in which a pixel array portion and a driving circuit are formed integrally on the same substrate.

When the driving circuit and the pixel array section are formed integrally, the ratio of the actual screen size to the external dimensions of the liquid crystal display device decreases as the area of the driving circuit increases.
Since the drive circuit is usually formed around the pixel array section, it is also called a frame. The smaller the frame area, the more the actual screen size can be increased, which is more desirable.

As one method for reducing the area of the frame, for example, Japanese Patent Application Laid-Open Nos. 1-246863 and 7-193251 disclose that the gate electrodes of the p-type TFT and the n-type TFT constituting CMOS are shared. A structure in which these TFTs are vertically stacked has been proposed.

[0005]

By the way, with the recent miniaturization of the semiconductor device, a decrease in the mobility of the device caused by hot carriers generated near the drain electrode of the MOS transistor has become a serious problem. . This problem,
In particular, this is remarkable in n-type TFTs,
As a result, this is a major factor that impairs the reliability of the liquid crystal display device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film transistor device capable of improving the integration degree while improving the reliability of the transistor.

[0007]

According to a first aspect of the present invention, there is provided a thin film transistor device formed on a substrate, comprising: a first transistor formed on the substrate; A second transistor formed on the upper surface of the first transistor with an insulating film in common with the gate electrode of the first transistor, and a drain / source end inside the first transistor is connected to the second transistor. This is self-aligned by the drain / source ends outside the two transistors.

The invention of claim 1 will be described with reference to FIGS. 1 and 2, for example. The "first transistor" corresponds to the NMOS transistor 21, the "second transistor" corresponds to the PMOS transistor 22, and the "channel region" corresponds to the first transistor. In the channel region 31,
The “LDD region” corresponds to the LDD region 7, respectively.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor device according to the present invention will be specifically described with reference to the drawings. The thin film transistor device described below, for example,
It is used in a driving circuit of a liquid crystal display device integrated with a driving circuit.

FIG. 1 is a manufacturing process diagram of an embodiment of a thin film transistor according to the present invention. Hereinafter, based on FIG.
The manufacturing process of the thin film transistor will be described step by step. First, as shown in FIG. 1A, an undercoat film 2 made of a silicon oxide film (SiOx) and a silicon nitride film (SiNx) is formed on a transparent insulating substrate 1. The undercoat film 2 protects the substrate 1 and also prevents diffusion of alkali ions from the substrate 1.

Next, an amorphous silicon thin film is deposited on the undercoat film 2 by, for example, a plasma CVD method. Next, the amorphous silicon thin film is heat-treated using a XeCl excimer laser device. As a result, the region irradiated with the laser light is crystallized to form the polycrystalline silicon film 3. At this time, by performing laser irradiation energy stepwise and performing irradiation multiple times, hydrogen in the amorphous silicon film can be efficiently removed, and ablation during crystallization can be prevented.

Next, as shown in FIG. 1B, the polycrystalline silicon film 3 is patterned by photolithography to form an active layer 4 of a thin film transistor. Next, the gate insulating film 5 made of a silicon oxide film is
It is formed by a CVD method. In addition, instead of the silicon oxide film,
A silicon nitride film may be formed. Or normal pressure CVD
A silicon oxide film may be formed by a method.

Next, as shown in FIG. 1C, a molybdenum-tungsten alloy film (hereinafter, referred to as MW) is formed by a sputtering method, and this film is patterned to form a gate electrode. At this time, a scanning line is formed at the same time. next,
Using the gate electrode 6 as a mask, low-concentration impurity ions (for example, phosphorus ions) are implanted by an ion doping method. As a result, LDD (Lightly Dope
d Drain) region 7 is formed.

Next, as shown in FIG. 1D, a gate insulating film 8 made of a silicon oxide film is formed. Next, after forming the polycrystalline silicon film 9, a resist 10 is further formed on the upper surface thereof, and the polycrystalline silicon film 9 is patterned by photolithography. Next, high-concentration impurity ions are implanted by ion doping using the resist 10 on which the polycrystalline silicon film 9 is patterned as a mask. By this ion implantation, source / drain regions 11 of the N-type MOS transistor are formed.
The LDD region 7 is formed adjacent to the channel region 31, and a region between the LDD regions 7 becomes a channel region 31.

Next, as shown in FIG. 1E, after a resist 12 is formed on the upper surface of the substrate, the resist 12 is patterned. Next, patterned resist 1
Using 2 as a mask, impurity ions (for example, boron ions) are implanted by an ion doping method. Thereby, the source / drain regions 13 of the P-type MOS transistor
Are formed, and a region between the regions 13 becomes a channel region 32.

Next, as shown in FIG.
After an interlayer insulating film 14 made of a silicon oxide film is formed on the gate electrode 6 by a CVD method or a normal pressure CVD method, patterning is performed.

Next, as shown in FIG. 2B, after forming an Al film by a sputtering method, the Al film is patterned and the source / drain electrodes 15 and 1 of both transistors 21 and 22 are formed.
6 is formed. At this time, signal lines are formed at the same time. Next, pS was applied on the patterned Al film by plasma CVD.
An iN passivation film 17 is formed to complete an array substrate.

Next, the array substrate and a counter substrate (not shown) on which a common electrode is formed are opposed to each other. A periphery of both substrates is surrounded by a sealing material made of epoxy resin, and a liquid crystal is injected between the two substrates. The liquid crystal display device is completed by sealing.

FIG. 3 is a plan view seen from the direction P in FIG. 2B, and a cross-sectional view taken along line AA in FIG. 3 corresponds to FIG. 2B. FIG. 4 is a conventional layout diagram in which an N-type MOS transistor 21 and a P-type MOS transistor 22 are formed adjacent to each other.

As can be seen by comparing FIG. 3 with FIG. 4, in the present embodiment, the gate electrode 6 of the N-type MOS transistor 21 and the P-type MOS transistor 22 is shared, so that the CMOS structure is The element formation area can be reduced.
Therefore, for example, when a driving circuit of a liquid crystal display device is formed using the thin film transistor device shown in FIGS. 1 to 3, the area for forming the driving circuit can be reduced, and the ratio of the actual screen size to the external dimensions of the liquid crystal display device can be reduced. Can be bigger.

Further, since the LDD region 7 is formed adjacent to the source / drain region 11 of the N-type MOS transistor 21, fluctuation of the threshold value due to generation of hot electrons can be prevented.

N-type MOS transistor 2 shown in FIGS.
1 and the P-type MOS transistor 22, a CMOS is formed by electrically connecting the gate electrodes 6 of both transistors to an input electrode, and forming the source / output of the N-type MOS transistor 21.
One of the drain electrodes and one of the source / drain electrodes of the P-type MOS transistor 22 are electrically connected to form an output electrode, and the other of the source / drain electrodes of the N-type MOS transistor 21 is set to the ground line L2. Transistor 22
Is connected to the power supply line L1.

At this time, if the power supply line L1 and the ground line L2 are too close to each other, the two lines are short-circuited and display on the liquid crystal display device becomes impossible. Therefore, the power line L1 and the ground line L2 are preferably separated from each other.

FIG. 5 is a layout diagram showing an example in which the thin film transistor device shown in FIGS. 1 to 3 has a CMOS structure and the power supply line L1 and the ground line L2 are arranged apart from each other. In FIG. 5, one side (the left side in FIG. 5) with the gate electrode 6 interposed therebetween.
Are connected to the ground line L2, and the source / drain electrodes of the P-type MOS transistor 22 disposed on the other side (the right side in FIG. 5) with the gate electrode 6 interposed therebetween. Is connected to the power supply line L1.

As described above, the ground line L2 connected to the source / drain electrodes of the N-type MOS transistor 21 and the P-type
Since the power supply line L1 connected to the source / drain electrodes of the MOS transistor 22 is disposed on both sides of the gate electrode 6, the distance between the power supply line L1 and the ground line L2 can be increased, and the power supply line L1 and the ground Short circuit failure with the line L2 does not occur. Therefore, the yield at the time of manufacturing the liquid crystal display device is improved.

In the above-described embodiment, the thin film transistor device for the driving circuit of the liquid crystal display device has been described as an example. However, the present invention can be widely used for other purposes. Available.

[0027]

As described above in detail, according to the present invention, since the first and second transistors are superposed on the substrate, the degree of integration of the transistors can be improved. In particular, if the present invention is applied to a drive circuit integrated type display device in which a drive circuit is formed around a pixel array portion, the formation area of the drive circuit can be reduced, and the ratio of the actual screen size to the external dimensions of the display device can be reduced. Can be bigger.

Further, by making the drain / source end inside the first transistor self-aligned with the drain / source end outside the second transistor, a threshold change due to generation of hot electrons can be prevented.
A transistor having uniform characteristics with little manufacturing variation can be formed.

Further, by using the LDD structure for the first transistor, a thin film transistor device with low power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of one embodiment of a thin film transistor according to the present invention.

FIG. 2 is a manufacturing process diagram following FIG. 1;

FIG. 3 is a plan view seen from a direction P in FIG. 2B.

FIG. 4 is a conventional layout diagram in which two transistors are formed adjacent to each other.

FIG. 5 is a layout diagram showing an example in which a power supply line and a ground line are arranged separately in a CMOS configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Undercoat film 3 Polycrystalline silicon film 4 Active layer 5 Gate insulating film 6 Gate electrode 7 LDD region 8 Gate insulating film 9 Polycrystalline silicon film 10 Resist 11 Source / drain region 12 Resist 13 Source / drain region 14 Interlayer insulating film 15, 16 Source / drain electrode 17 Passivation film

Claims (5)

[Claims] A thin film transistor device formed on a substrate, wherein a first transistor formed on the substrate has a gate electrode common to the first transistor, and an insulating film is formed on an upper surface of the first transistor. And a second transistor formed through the first transistor, wherein an inner drain / source end of the first transistor is self-aligned with an outer drain / source end of the second transistor. Thin film transistor device. 2. The thin film transistor device according to claim 1, wherein said first transistor is an N-type MOS transistor, and said second transistor is a P-type MOS transistor. 3. An LDD (Lightly Doped) between a drain / source end inside the first transistor and a channel region.
The thin film transistor device according to claim 1, wherein a drain region is formed. 4. The first and second transistors are connected in series to form a CMOS, and the first and second transistors are arranged on one side with a common gate electrode of the first and second transistors interposed therebetween. One of the drain / source electrodes of one transistor is connected to a ground layer, and one of the drain / source electrodes of the second transistor disposed on the other side of the gate electrode is connected to a power supply layer. The thin film transistor device according to claim 1. 5. The semiconductor device according to claim 1, wherein said substrate is a glass substrate, and said first and second transistors are polycrystalline silicon thin film transistors.
A thin film transistor device according to any one of the above.